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Roberto Frazzoli
Roberto Frazzoli
Roberto Frazzoli is a contributing editor to EDACafe and a seasoned freelance journalist specialized in electronics. His weekly contribution to EDACafe – since early 2019 - includes news updates, coverage of major industry events, special reports, and interviews. Prior to joining EDACafe, Roberto … More »

Intel process and architecture updates; AI in EDA attracting investors; Foxconn to add SiC and MEMS offering

 
August 27th, 2021 by Roberto Frazzoli

Catching up on some of the news from the last four weeks or so, Intel stands out with its late-July and mid-August announcements which we will briefly recall below – along with several more news from various areas. But first, a quick update on the Nvidia-Arm deal: according to the UK Government’s Competition and Markets Authority (CMA), this acquisition would “lead to a realistic prospect of a substantial lessening of competition”. Another quick update about GlobalFoundries, which – according to Reuters – has filed confidentially with U.S regulators for an initial public offering (IPO) in New York.

EDA updates: Cadence, Motivo, Avishtech

Anirudh Devgan to become Cadence CEO. Current Cadence CEO Lip-Bu Tan will transition to the role of executive chairman on December 15, 2021, with President Anirudh Devgan assuming the role of president and CEO at that time. Devgan has also joined the Cadence Board of Directors.

AI-enabled EDA tools developer Motivo raises $12 million financing. The Series A financing round is led by Intel Capital and follows earlier seed rounds of $8 million. Motivo’s technologies accelerate chip design utilizing a “learning-on-graph” methodology for automated data-driven feature extraction. According to the company, Motivo’s M-Graph and other explainable AI technologies can be applied across the entire design flow, from RTL code to layout geometries. With this approach, Motivo aims to compress the design-to-manufacturing process from years to months.

Predicting fiber-weave related skew on differential pairs. EDA startup Avishtech has enhanced its Gauss Stack PCB stack-up design and simulation toolset with the capability of predicting the maximum fiber-weave related skew on differential pairs. As explained in a press release, glass weave-induced skew in differential pairs is caused when a trace runs over a glass fiber for some distance and then between glass fibers. When this happens, the dielectric constant varies substantially, causing significant variations in impedance and velocity along the trace. When the two members of a differential pair travel over the weave pattern these variations may not be equal in both members.

Intel renaming process nodes and announcing new architectures

On July 26, Intel unveiled its updated process technology roadmap. Highlights include renaming of its process nodes – in particular, the “10nm Enhanced SuperFin” process is now called “Intel 7” – and the preannouncement of a future transistor architecture called RibbonFET, using power vias on the bottom side of the wafer. A fact sheet on these announcements is available here.

On August 19 at its Architecture Day, Intel introduced several innovations across its whole processor range – including two new x86 core architectures; Intel’s first performance hybrid architecture, code-named “Alder Lake,”; “Sapphire Rapids,” the next-generation Intel Xeon scalable processor for the data center; new infrastructure processing units; and upcoming graphics architectures, including the Xe HPG and Xe HPC microarchitectures, and Alchemist and Ponte Vecchio SoCs. A ten-page fact sheet summarizing the innovations introduced is available here. Some of the highlights include a new scheduling technology called Intel Thread Director, built directly into the hardware, which provides low-level telemetry on the state of the core and the instruction mix of the thread, empowering the operating system to place the right thread on the right core at the right time; the graphics SoC now called Alchemist, featuring a new upscaling technology dubbed XeSS that uses deep learning to synthesize images that are close to the quality of native high-resolution rendering; and the introduction of Intel’s first ASIC Infrastructure Processing Unit – as opposed to FPGA-based IPUs. Some of the processors announced at the Architecture Day are examples of Intel’s new strategy of mixing and matching chiplets from different foundries – both from its own fabs and from TSMC – and assembling them using its embedded multi-die interconnect bridge (EMIB) packaging technology.

Credit: Intel

More processor updates: IBM, Baidu

IBM chip to enable real-time AI-based fraud detection. The upcoming new Telum Processor contains on-chip acceleration for AI inferencing while a transaction is taking place, to help address fraud in real-time in banking, finance, trading, insurance applications and customer interactions. According to IBM, with the traditional approach complex fraud detection often cannot be completed in real-time due to latency requirements. The dual-chip module design contains 22 billion transistors. A Telum-based system is planned for the first half of 2022.

New generation of Baidu’s Kunlun processor. The new Kunlun II “offers 2-3 times more processing power than the previous generation, using the world’s leading 7nm process and equipped with Baidu’s own second-generation XPU architecture,” the company claimed in a press release. The announcement was made on the occasion of the Baidu World 2021 conference.

More news: Foxconn, STMicroelectronics, Seoul Viosys

Foxconn enters the semiconductor business. Taiwanese EMS giant Foxconn has bought Macronix’s 6-inch wafer fab and equipment in Hsinchu Science Park. The move “officially signals Foxconn’s entry into the manufacture and development of wide band gap semiconductors, especially SiC, paving the way for a long-term commitment to semiconductor development”, the company declared in a press release. In addition to SiC Power MOSFETs, Foxconn will also manufacture silicon wafer products, such as MEMS.

STMicroelectronics starts manufacturing 200mm SiC wafers. Silicon-Carbide bulk wafers for prototyping next-generation power devices are being manufactured in Norrköping, Sweden – a facility that used to be the headquarter of Norstel, which ST acquired in 2019. ST currently manufactures its STPOWER SiC products on two 150mm wafer lines in its fabs in Italy and Singapore.

Micro LED advancements. Seoul Viosys, a subsidiary of Seoul Semiconductor, and University of California, Santa Barbara succeeded in developing blue and green micro-LEDs with 1 μm diameter, and addressed issues related to red micro LEDs of less than 70 μm, which previously could not be mass-produced due to a decrease in External Quantum Efficiency (EQE). Seoul Viosys expects these achievements to be a game-changer in the global display industry.

Acquisitions

Marvell will acquire Innovium in an all-stock transaction. The move is focused on Innovium’s Teralyinx switching architecture targeted at cloud-scale data centers.

Canadian ADAS vendor Magna will acquire Swedish automotive safety specialist Veoneer.

Upcoming events

The Single Event Effects Symposium coupled with the Military and Aerospace Programmable Logic Devices (SEE/MAPLD) will be held as a virtual meeting from August 31 to September 2.

Silicon Labs’ “Works With” virtual conference on IoT will take place next September 14 and 15.

The AI Hardware Summit is currently scheduled as an in-person event at the Computer History Museum in Mountain View from September 13 to 15.

Strategic Materials Conference (SMC 2021) will take place as a live event from September 27 to 29 in San Jose, CA.

The 2021 RISC-V Summit will co-locate with the 58th Design Automation Conference (DAC), in San Francisco from December 6 to 8.

Semicon Taiwan 2021 has been rescheduled to December 28-30, with a three-month experience set to begin in September with five live online forums.

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