This week EDACafe takes a quick look at the 2021 edition of the Linley Fall Processor Conference, organized by technology analysis firm The Linley Group at a physical venue in Santa Clara, CA, and followed by a virtual event. Besides updates on deep learning accelerators, the conference also covered ‘conventional’ processing solutions and some other types of IP. This article will only provide a general overview of the event; full content can be accessed from the conference website, downloading the proceedings (presentations slides) for free.

AI trends: bigger training workloads, segmentation of the edge-AI market

In his opening keynote, Linley Group’s Principal Analyst Linley Gwennap reiterated the key concepts from last Spring processor conference, adding updates on the recent AI trends. Among them, the size of NLP models keeps growing: Google’s Switch Transformer has 1.6 trillion parameters. To train ever-larger neural networks, Cerebras and Tesla are using wafer-scale technology and other innovations. In the datacenter, Nvidia is finding tougher competition from Qualcomm AI 100 and forthcoming Intel Ponte Vecchio. According to Gwennap, Nvidia still leads in performance, but not in efficiency. As for edge-AI, this market is fragmenting into high-end chips for camera-based systems and low-power chips for simple sensors. The conference also saw the participation of TechInsights – the Canadian reverse engineering firm that has recently acquired The Linley Group – with a presentation on the performance gap between CPU and main memory. Among other findings, TechInsights analysts concluded that SRAM cell size scaling trend is getting worse than Logic Standard Cell because SRAM cell does not have DTCO (Design Technology Co-Optimization) scaling options.

Read the rest of A quick look at the 2021 Linley Fall Processor Conference

Global scrutiny of the Nvidia-Arm deal continues: adding to a list of other authorities, European Union regulators have reportedly opened an investigation over concerns of limited competition. The EU Commission said Nvidia had offered concessions to address preliminary concerns, but that they weren’t enough. A decision from European regulators is expected within March 15. As for the other news updates this week, several of them concern autonomous vehicles – including two acquisitions of radar specialist companies.

Autonomous driving tech market is consolidating

According to market intelligence firm CB Insights, a few key players are emerging in autonomous driving technology, and the market is consolidating around major companies like Waymo and Aurora. Every round backed by top venture capital firms in the AV market over the last two years has been Series C or later. This indicates that – as the AV market consolidates – the top VCs monitored by CB Insights “are focusing on the winners, seeing stronger potential for leading self-driving developers rather than early-stage companies.” Another sign of consolidation is the move from many deals to just a few big ones: total funding to autonomous driving companies spiked in 2018, but “since then, deal count has declined significantly as total funding continues to rise.” The majority of the funding by top VCs in AVs over the last two years “has come from just two mega-rounds ($2.25B in 2020 and $2.5B in 2021) to Waymo.” According to CB Insights, the top venture capital firms are now backing companies working on simulation and training, developing the full self-driving stack, enhancing mapping and localization, and more. “Total equity funding to the space has already eclipsed $12B in 2021, up more than 50% from all of 2020,” the analysts elaborated. The selected top VCs monitored by CB Insights “have participated in a record-breaking $3.85B of total funding to autonomous driving companies so far in 2021, with the total projected to be above $5.1B by year end if the trend continues.”

“Smart Money” refers to a group of top VCs as defined by CB Insights.
Credit: CB Insights

Read the rest of AV market consolidation; Indy AV race; solid-state batteries; acquisitions

Chips built using 2-nanometer processes will enter volume production in 2025; this, at least, is what we can expect based on the roadmap updates recently provided by both Samsung Foundry and TSMC. For the 2-nanometer node, the South Korean company will adopt its version of the gate-all-around transistor architecture; TSMC is also considering GAA, but has not committed to it yet. More news this week include a 60-billion transistor chip from Alibaba, and a multi-pronged Arm initiative meant to boost the IoT market. But first, a couple of EDA updates.

Ansys adds a charging/discharging simulation solution

Ansys has added EMA3D Charge to its simulation solution portfolio. Developed by Colorado-based Electro Magnetic Applications company, EMA3D Charge enhances predictive accuracy for charging and discharging events that can have an impact on safety for a wide range of electric/electronics products. Leveraging Ansys SpaceClaim, the solution combines CAD import, design and simplification, simulation setup and meshing, and result generalization and visualization into one solver technology. According to Ansys, EMA3D Charge fills a need in a marketplace in which no other simulation product exists, providing a unified end-to-end workflow.

Cadence to speed up ISO 26262 and IEC 61508 certification

Cadence has announced the Cadence Safety Solution, a new offering featuring integrated analog and digital safety flows and engines for faster ISO 26262 and IEC 61508 certification. Targeting safety-critical applications – such as automotive and aerospace – the solution includes a new failure modes, effects, and diagnostic analysis (FMEDA) offering called the Cadence Midas Safety Platform, allowing to perform FMEDA-driven analog and digital verification of safety-critical semiconductors.

Read the rest of TSMC and Samsung Foundry roadmaps; new Alibaba processors; Arm Virtual Hardware for IoT

Geopolitical tensions made headlines over the past few days, with Chinese President Xi Jinping in his recent speech reportedly vowing to pursue reunification with Taiwan. Needless to say, this news is also relevant to the semiconductor industry as Taiwan is homeland of the world’s largest foundry. Let’s now move to this week’s updates, which include a quick look at some companies based in mainland China attracting significant investments.

GlobalFoundries to go public

GlobalFoundries has publicly filed a registration statement with the U.S. Securities and Exchange Commission (the SEC) relating to the proposed initial public offering of its ordinary shares. GF has applied to list on the Nasdaq Global Select Market under the ticker symbol GFS.

Intel offers a Risc-V-based soft processor for its FPGAs

The new generation of Nios, the soft processor for Intel FPGAs, is based on the open-source Risc-V Instruction Set Architecture. Called Nios V, the family currently includes a micro controller – Nios V/m – based on Risc-V: RV32IA, with atomic extensions, 5-stage pipeline, and AXI4 interfaces. Future releases will include a general-purpose processor, an application-class processor, and a Linux-capable processor. Benefits cited by Intel include the open-source ecosystem – toolchains, debuggers, real-time operating system – and performance improvements over the Nios II/e processor. The new Nios V soft processor is available in the Intel Quartus Prime Pro Edition Software starting with version 21.3.

Read the rest of GloFo to go public; Intel’s Risc-V-based soft processor; Chinese investments in Q3; pixel-shift for smartphones

Catching up on some of the news from the last couple of weeks or so, let’s briefly recall that European Union politicians have started discussing about a plan to support the semiconductor industry in the Old Continent. The President of the European Commission, Ursula von der Leyen, has recently preannounced a European Chips Act. “We need to link together our world-class research, design and testing capacities,” she said in her recent State of the Union speech. “We need to coordinate EU and national investment along the value chain. The aim is to jointly create a state-of-the-art European chip ecosystem, including production. That ensures our security of supply and will develop new markets for ground-breaking European tech. (…) We are world leaders. So let’s be bold again, this time with semi-conductors.” Additional details on the upcoming European Chips Act have been provided by European Commissioner Thierry Breton in this blog post, quoting Imec, CEA-Leti and Fraunhofer as key European assets. “I believe that we should explore setting up a dedicated European Semiconductor Fund,” he wrote. “With the European Chips Act, our tech sovereignty is within reach.”

Copyright European Union, 2021. Photographer: Christophe Licoppe

EDA/IP updates: Cadence, MathWorks, Arteris IP, Bluespec, Sigasi

The new Cadence Helium Virtual and Hybrid Studio is a platform that accelerates the creation of virtual and hybrid prototypes of complex systems. According to Cadence, Helium Studio makes verification with a virtual or hybrid model of the SoC orders of magnitude faster than verification with a pure RTL model, and it also enables early software bring-up before the RTL is available. Natively integrated with the Cadence verification engines – including Palladium Z2, Protium X2 and Xcelium – the new Helium Studio accelerates system development by verifying embedded software/firmware on pure virtual and hybrid configurations even when the RTL is not ready.

Read the rest of New MathWorks release; Arteris IP to go public; compact Risc-V IP; Arm-based servers for AI workloads; new Loihi chip

Artificial Intelligence updates – in terms of new IP and new startup funding – make up a significant part of this week’s news roundup, while other recurring themes include optics/photonics applications and IoT security.

AI updates: Cadence, Deep Vision, Axelera

Cadence has unveiled its Tensilica AI Platform for AI SoC development, including three product families for the low, mid and high end. Built upon the Tensilica DSPs, the Tensilica AI Platform adds a new companion AI neural network engine (NNE) and neural network accelerators (NNAs). The “AI Base” family includes the Tensilica HiFi DSPs and ConnX DSPs, combined with AI instruction-set architecture extensions. The “AI Boost” family adds a companion NNE, initially the Tensilica NNE 110 AI engine, which scales from 64 to 256 GOPS. The “AI Max” family encompasses the Tensilica NNA 1xx AI accelerator family—currently including the Tensilica NNA 110 accelerator and the NNA 120, NNA 140 and NNA 180 multi-core accelerator options—which integrates the AI Base and AI Boost technology. The multi-core NNA accelerators can scale up to 32 TOPS, while future NNA products are targeted to scale to 100s of TOPS. Targeting intelligent sensor, IoT, audio, mobile vision/voice AI and ADAS applications, the Tensilica AI Platform features a common software platform and – according to Cadence – delivers optimal power, performance and area.

Deep Vision has received $35 million in a Series B financing round led by Tiger Global. Deep Vision’s AI processor, named ARA-1, targets camera-based applications such as smart retail, driver-monitoring systems, smart city, drones, and factory automation. The company’s processor also provides natural language processing capabilities.

Read the rest of AI startups; microLED-based interconnect; silicon nitride photonics; cloud-native automotive software; new solid-state LiDAR

No shortage of interesting news this week – both from the industry and from academia – still it’s worth devoting some space to a Tesla event that took place last month, showing how system-level assembly technologies can make a difference for supercomputers.

Fab and foundry updates: Intel, SMIC, X-Fab, Samsung

Intel’s CEO Pat Gelsinger has reportedly said the company will invest up to €80 billion over the next decade to build new chip fabs in Europe.

According to the Wall Street Journal, SMIC is teaming up with the Shanghai government to build an $8.87 billion chip production line in the city.

Germany-headquartered X-Fab Silicon Foundries is now able to support volume heterogeneous integration via Micro-Transfer Printing (MTP), thanks to a licensing agreement with X-Celeprint. Technologies that may be combined include SOI, GaN, GaAs and InP, as well as MEMS. X-Celeprint’s pick-and-place MTP technology stacks and fans-out ultra-thin dies.

Samsung Electronics has reportedly chosen the city of Taylor, Texas, as the site for its planned $17 billion new chip plant – which will be four times larger than Samsung’s existing fab in Austin. To attract the investment, the city of Taylor has reportedly offered Samsung a $314 million worth of tax breaks for the next ten years.

Source: official City of Taylor website

Read the rest of New fabs; Tesla training system; GaN CMOS; CUDA on Risc-V; Y Combinator startups