Several updates concerning U.S.-China tensions have been in the news over the last few days. Risc-V is another major theme of this news roundup, with product announcements from the recent Risc-V Summit. And one more AI startup is raising the bar for energy efficiency.
Will the ‘chip war’ escalate hitting older nodes?
While export controls on Western technologies have so far focused on the most advanced process nodes, the ‘chip war’ between the U.S. and China could potentially escalate and hit older nodes, according to a TechInsights analyst quoted by Reuters. The premises for this analysis can be found in two press reports: on the one hand, China is reportedly working on a $143 billion support package for its semiconductor industry, to counter U.S. moves aimed at slowing its technological advances; on the other hand, Chinese foundry SMIC is reportedly ramping up production of 28-nanometer chips, an old node still widely used in automotive, weapons and IoT applications. While subsidies would likely benefit Chinese equipment manufacturers – such as Naura, Advanced Micro-Fabrication Equipment and Kingsemi – the concern of TechInsights is that SMIC and other chipmakers in China could use government subsidies to sell 28-nanometer chips at a low price, flooding this market segment and wiping out global competition.
As the industry celebrates the 75th anniversary of the invention of the transistor, geopolitical issues keep making news with Taiwan-headquartered TSMC stepping up its commitment to U.S. fabs. Several updates this week concern technological advancements presented at the IEDM conference.
TSMC to increase its Arizona investment
TSMC has announced that in addition to its Arizona’s first fab, which is scheduled to begin production of N4 process technology in 2024, it has also started the construction of a second fab which is scheduled to begin production of 3-nanometer process technology in 2026. The overall investment for these two fabs will be approximately US$40 billion, representing the largest foreign direct investment in Arizona history and one of the largest foreign direct investments in the history of the United States. TSMC Arizona’s two fabs are expected to directly hire 4,500 employees and, when complete, to manufacture over 600,000 wafers per year. This investment has reportedly sparked concerns in Taiwan, prompting the local government to reassure on TSMC’s commitment to the island. However, according to another report TSMC is planning to move all its 3-nanometer production to the U.S., which would enable Apple to equip its future iPhone 15 models with a new 3-nanometer processor made in the United States.
Will the U.S. ‘CHIPS and Science Act’ benefit fabless companies? As noted by a report just released by the Semiconductor Industry Association (SIA) and the Boston Consulting Group, the recently passed U.S. support plan will provide public funding for semiconductor manufacturing, but not for design. The report finds that a federal investment in semiconductor design and R&D of $20 to $30 billion through 2030 – including a $15 to $20 billion for an investment tax credit for semiconductor design – will help maintain long term U.S. chip design leadership.
Semiconductor capex to drop in 2023 – forecast
Despite the booming demand in early 2022, market research firm IC Insights forecasts a -19% drop in total worldwide semiconductor capital industry spending in 2023, “the steepest decline since the global financial meltdown in 2008-2009.” This forecast already considers the impact of the U.S ‘CHIPS and Science Act’: “IC Insights does not expect a boost to semiconductor capital spending from the $52 billion in grants that will be given to U.S. semiconductor suppliers as part of the U.S. CHIPS and Science Act that was passed earlier this year. Rather, IC Insights believes that most U.S. semiconductor producers that receive this money will use it to replace what they would have spent if not receiving the grant. In other words, the CHIPS and Science Act money is not expected to be ‘additive’ funding to planned semiconductor industry spending, but instead is likely to replace the money a semiconductor producer was going to budget if CHIPS and Science Act funding was unavailable,” the market research firm maintains.
This year’s fall edition of the Linley Processor Conference – held on November 1 and 2 in Santa Clara, California – was, as usual, a good observation point to keep abreast of trends and products in neural network acceleration. In this article we will provide a very quick overview of part of the conference, focusing on the keynote given by Linley Gwennap and on the presentations from the companies that addressed AI acceleration topics. The event, of course, offered many more presentations concerning ‘conventional’ (non-AI) processors and other processing-related themes, which we will not cover here.
Linley Gwennap’s keynote: trends in AI acceleration
In his keynote, Linley Gwennap – principal analyst at TechInsights – noted that the growth of AI model size has slowed, as training has become increasingly resource-intensive: for example, training the GPT-3 language processing model takes 1,024 Nvidia A100 GPUs over one month. Rapid growth of AI model size has been enabled by moving training to large processing clusters, but cluster size is topping out for cost reasons: 1,024 GPUs cost approximately $25 million. As a result, essentially there has been no growth in largest trained models over the past year, and recent progress focuses on models with less compute per parameter. Future growth of AI model size will be paced by hardware progress, e.g. the availability of new Nvidia H100 clusters.
Geopolitical tensions keep making headlines, with Japan trying to catch up on advanced nodes capabilities to gain more independence from foreign suppliers. Western world investments in new fabs continue, with Infineon planning for the construction of a factory for 300-millimeter analog/mixed-signal and power semiconductors in Dresden, Germany. More news this week include three interesting academic research works.
Japanese government to subsidize a new domestic chipmaker
As reported by The Japan Times, eight major Japanese companies have jointly invested to launch a new firm, named Rapidus, tasked with developing 2-nanometer chips by 2027, in collaboration with IBM. The eight companies – Toyota, Sony, NTT, SoftBank, Kioxia, Denso, NEC and MUFG Bank – invested a total of ¥7.3 billion ($52 million) to form the new venture, which is chaired by Tetsuro Higashi, former president of chip equipment firm Tokyo Electron. The Japanese government plans to provide the new company with ¥70 billion ($500 million) in subsidies, backed by a second extra budget. Japan will also create a new body for chip research and development called ‘Leading-edge Semiconductor Technology Center’ (LSTC) by the year’s end, consisting of Japan’s major research bodies and universities. Reportedly, analysts are skeptical about the success of Rapidus, as the financial support promised by the Japanese government so far is much smaller than the amounts set out by the U.S. and the European Union for their ‘chips acts’, $52.7 billion and €43 billion ($45 billion) respectively.
Taiwanese foundry TSMC and its collaboration with major EDA partners make up a large part of this week’s news roundup. Other foundries are in the news as well. But first, a quick look at some market data and investment trends.
EDA record revenues
Record numbers are being reported for the Electronic System Design industry: as announced by the ESD Alliance, revenue increased 17.5% from $3,191.4 million in Q2 2021 to $3,748.7 million in Q2 2022. The four-quarter moving average, which compares the most recent four quarters to the prior four, rose 15.3%. As noted by Wally Rhines, the EDA industry in Q2 2022 posted the highest year-over-year increase in over a decade, and all product categories and geographic regions recorded growth in the quarter.
Fab capex reduction
Several chipmakers, however, are cutting their planned capital expenditure citing weaker consumer demand. Among them Taiwanese foundry UMC, which will reportedly reduce its capex by almost a fifth, and South Korean memory maker SK hynix, which has decided to cut its investment next year by more than 50% YoY, citing an unprecedented deterioration of the market conditions in the semiconductor memory industry as uncertainties in the business environment continue.
New export controls have been in the spotlight over the past few days. Other news this week include several EDA updates and some interesting academic research.
New U.S. controls on export to China
The U.S. Government is implementing new export controls on advanced computing and semiconductor manufacturing items to the People’s Republic of China. Details of the new rules can be found here and here. According to Bloomberg, these additional restrictions will not apply to the China-based fabs owned by South Korean chipmakers SK Hynix and Samsung. In fact, SK Hynix Inc has reportedly said it has received authorization from the U.S. Department of Commerce to receive chip equipment needed for its chip production facilities in China for one year, without seeking additional licensing requirements.
Cadence Certus aims to accelerate design closure
Cadence has announced the new Certus Closure Solution environment, to automate and accelerate the complete design closure cycle – from signoff optimization through routing, static timing analysis and extraction. Key to acceleration is a massively parallel and distributed architecture enabling concurrent processing. According to Cadence, the solution supports the largest chip design projects with unlimited capacity while improving productivity by up to 10X versus current methodologies and flows.
Plenty of news from the whole ICT-semiconductor ecosystem this week, some of them with a common underlying theme: the advent of chiplet-based 3D devices. Let’s start with some EDA updates.
Synopsys’ ‘streaming fabric’ for silicon lifecycle management
Synopsys has announced a streaming fabric technology aimed to shorten both silicon data access and test time – by up to 80%, according to the company – while also minimizing excessive power. Generated by Synopsys TestMAX DFT tool and part of Synopsys’ silicon lifecycle management flow, the new streaming fabric is an on-chip network that transports silicon data to and from multiple design blocks and multi-die systems. According to Synopsys, the fabric calls for minimal planning effort and has a limited physical impact on design. Additionally, a new power estimation technology incorporated in Synopsys TestMAX ATPG solution more accurately determines power drawn at data application time.
Synopsys’ new ECO solution
Synopsys has also announcedPrimeClosure, a golden signoff ECO (engineering change order) solution that addresses lengthy engineering design closure times. According to the company, early customers have achieved up to 45% better timing, up to 10% better power, up to 50% fewer ECO iterations and up to 10x higher design productivity compared to traditional ECO flows. PrimeClosure has direct access to incrementally enabled placement, routing, extraction, physical verification, equivalence checking and signoff technologies from the other Synopsys tools, and is integrated with Ansys RedHawk-SC digital power integrity signoff solution, enabling to account for and fix up to 50% of late-stage dynamic voltage drop violations and maximize energy efficiency without impacting chip timing.
New developments have emerged on the implementation of the U.S ‘CHIPS and Science Act’. More news this week include both Nvidia and Qualcomm advocating the unification of automotive electronic functions in a single system-on-chip. But first, an EDA update.
Synopsys’ unified emulation and prototyping system
Synopsys has announced what it claims is “the industry’s first” unified hardware system for emulation and prototyping, based on its ZeBu EP1 emulation system. Unification enables a single verification hardware system to be used throughout the entire chip development lifecycle. According to Synopsys, users of the ZeBu EP1 system have achieved 19 MHz emulation and 100 MHz prototyping clock performance, enabling them to run large amounts of software pre-silicon and accelerate project schedules. The unified hardware system allows users’ verification and software development requirements to drive how and when to shift capacity between emulation and prototyping, rather than having to estimate early on how much of each resource might be needed.
U.S. CHIPS Act updates: leadership team, innovation coalition
The U.S. government has announced the leadership team which will be responsible for the implementation of the CHIPS and Science Act. Members of the team are Ronnie Chatterji, Michael Schmidt, Eric Lin, Todd Fisher, Donna Dubinsky, and J.D. Grom. Individual roles and bios are detailed in this press release.
More than 100 businesses, startups, universities and nonprofits have formed the American Semiconductor Innovation Coalition (ASIC) with the specific goal of being selected by the Department of Commerce as the partner of choice for the newly created ‘National Semiconductor Technology Center’ and ‘National Advanced Packaging Manufacturing Program’ – both funded through the recently passed ‘CHIPS and Science Act’. Among others, ASIC members include AMD, Analog Devices, Ansys, Applied Materials, Cadence, DuPont, GlobalFoundries, IBM, KLA, Microsoft, Micron, MIT, Nvidia, Samsung, Siemens EDA, Synopsys, Texas Instruments. Some of the coalition members are headquartered in Europe, such as ASML, CEA-Leti, Fraunhofer, imec and Yole Développement. In terms of academic institutions, the ASIC member list currently published on the coalition website does not include neither Stanford University nor UC Berkeley. ASIC claims the ability to stand up an NSTC innovation hub in as little as six months. Among its key capabilities, the coalition mentions the already existing Albany NanoTech Complex.
According to a Reuters report, the Biden administration plans next month to broadencurbs on U.S. shipments to China of AI chips and semiconductor equipment. The new regulations would be based on restrictions communicated in letters earlier this year to KLA, Lam Research and Applied Materials. The letters forbade these companies from exporting chipmaking equipment to Chinese factories that produce chips with sub-14 nanometer processes unless the sellers obtain Commerce Department licenses. Some of the sources quoted by Reuters said the regulations would likely include additional actions against China.
Cadence new verification platform
The new Cadence Verisium AI-Driven Verification Platform is a suite of applications leveraging big data and AI to optimize verification workloads, boost coverage and accelerate root cause analysis of bugs. Verisium is built on the new Cadence Joint Enterprise Data and AI (JedAI) Platform and is natively integrated with the Cadence verification engines. The initial suite in the Verisium platform includes multiple apps using machine learning to automate tasks such as regression failure triage; pinpoint potential bug hotspots caused by source code revisions; analyze waveforms looking for the root cause of a test failure; predict which source code check-ins are most likely to have introduced failures. More Verisium apps offer a debug solution from IP to SoC and from single-run to multi-run; and full flow IP and SoC-level verification management.
