New chiplet description standard; AMD’s AI acceleration roadmap; Ultra Accelerator Link; 3-layer CMOS image sensors

Some of this weeks’ news updates are coming from Computex, Taiwan’s computer expo, which this year offered speeches from a lineup of semiconductor CEOs including AMD’s Lisa Su, Nvidia’s Jensen Huang, Intel’s Pat Gelsinger, Arm’s Rene Haas, and Qualcomm’s Cristiano Amon. While Computex isn’t the only thriving show in the IT world – just think of CES or MWC – it’s interesting to notice that its American and European counterparts died years ago. Las Vegas’ Comdex was held only until 2003; Hanover’s CeBit survived until 2018.

Ansys simplifies cloud-based simulation on Azure

Ansys has launched “Ansys Access on Microsoft Azure” to enable seamless deployment of pre-configured Ansys products on Azure cloud platform infrastructure. According to the company, Ansys’ customers using their own Azure subscription with existing Ansys licenses can now benefit from a more scalable, secure, and cost-effective approach to running HPC simulations in the cloud.

As Ansys explained in a press release, there are many challenges that need to be addressed when using simulation in the cloud. These include validating on-premises workloads that have been shifted to the cloud, the ongoing work to deploy and test new virtual machines and configuring adjacent cloud-based infrastructure in a cost-effective manner. “Ansys Access on Azure” addresses these challenges by delivering pre-tested and configured Ansys applications updated with each major release and aligned to a curated set of recommended VMs and HPC infrastructure. According to Ansys, this simplifies implementation for IT departments, giving them better control over cost.

New chiplet description standard

JEDEC has published a new release of the JEP30 PartModel Guidelines – including reference documents and related XML Schema files – that combines the capabilities and open standards of OCP’s Chiplet Data Extensible Markup Language (CDXML) into the JEDEC’s JEP30 PartModel Guidelines. This integration expands the capability of the PartModel to enable chiplet builders to also provide standardized chiplet part descriptions to their customers electronically. This advancement opens the door to automating System in Package (SiP) design and assembly using chiplets. The chiplet descriptions encompass crucial information for SiP builders, including thermal properties, physical and mechanical requirements, behavior specifications, power and signal integrity properties, testing in-package and security parameters. This latest release also enables the PartModel to represent Die-Arrays, scalable to support multiple depths of hierarchical nested arrays and billions of bumps.

AMD unveils its AI acceleration roadmap

At Computex 2024 in Taiwan, AMD unveiled a multiyear, expanded Instinct accelerator roadmap which will bring an annual cadence for new product generations – in an ongoing effort to compete against Nvidia. The updated roadmap starts with the new Instinct MI325X accelerator, which will be available in Q4 2024. The MI325X will bring 288GB of HBM3E memory and 6 terabytes per second of memory bandwidth, and will use the same industry standard Universal Baseboard server design used by the MI300 series. According to AMD, this accelerator will have industry leading memory capacity and bandwidth, 2x and 1.3x better than the competition respectively, and 1.3x better compute performance than competition.

Following that, the Instinct MI350 series, powered by the new AMD CDNA 4 architecture, is expected to be available in 2025 bringing up to a 35x increase in AI inference performance compared to Instinct MI300 Series with CDNA 3 architecture. The first product in the MI350 Series, the MI350X accelerator, will use the same industry standard Universal Baseboard server design as other MI300 Series accelerators and will be built using a 3-nanometer process technology. It will support the FP4 and FP6 AI datatypes and have up to 288 GB of HBM3E memory.

Next step in the AMD roadmap is the MI400 series, expected to arrive in 2026, which will be based on the AMD CDNA “Next” architecture.

Nvidia’s CEO Jensen Huang also announced the adoption of a yearly frequency for new product generations in his speech ahead of Computex: “Our company has a one-year rhythm. Our basic philosophy is very simple: build the entire data center scale, disaggregate and sell to you parts on a one-year rhythm, and push everything to technology limits,” he said.

New datacenter connectivity standard proposed

AMD, Broadcom, Cisco, Google, Hewlett Packard Enterprise (HPE), Intel, Meta and Microsoft have formed the UALink Consortium to develop the Ultra Accelerator Link (UALink), a new, open industry standard dedicated to advancing high-speed and low latency communication for scale-up AI systems linking in data centers. The 1.0 specification – expected to be available in Q3 of 2024 – will enable the connection of up to 1,024 accelerators within an AI computing pod and allow for direct loads and stores between the memory attached to accelerators, such as GPUs, in the pod. Notably, as of today the UALink Consortium does not include Nvidia.

Three-layer IC stacking paves the way to AI-enabled CMOS image sensors

At the recent ECTC conference in Denver, French research institute CEA-Leti reported about its advancements in 3D stacking technologies enabling a new generation of CMOS image sensors with embedded AI capabilities, for image processing and identification of elements in the scene. Key to the achievement is the combination of hybrid bonding and high-density Through-Silicon Vias. This enabled the construction of a three-layer test vehicle that features two embedded Cu-Cu hybrid-bonding interfaces (face-to-face and face-to-back), with one wafer containing high-density TSVs. Details of these technologies were presented in three papers authored by CEA-Leti researchers.

Further reading

A Washington Post article authored by three analysts who cover the so-called U.S.-China “chip war” is urging the U.S. to prioritize revolutionary research, instead of incremental improvements of existing technologies. The authors are asking the U.S. National Semiconductor Technology Center (NSTC) – the organization tasked to deploy up to $11 billion in R&D funds allocated by the U.S. Chips Act – to replicate what DARPA did in the 1970s: supporting the research for far-reaching advances.

The Washington Post article spurs reflections on the differences and similarities between the “cold war” era – when DARPA played a key role in tech research because technological supremacy was considered a military issue – and the present situation. The U.S. Chips Act and its European counterpart were designed in the wake of the chip shortage that stopped carmakers’ plants, but – since then – semiconductors have gradually become a national security issue, with export restrictions being placed on an increasing number of Western tech products, on fear of military-related applications in China. Are the Chips Acts of the world still up-to date? Given their industrial DNA, could these subsidy plans actually pivot their focus from incremental improvements to revolutionary research?

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