Risc-V starts attracting attention in the context of U.S.-China “chip war”: a bipartisan group of eighteen U.S. lawmakers that includes five Democrats is reportedly asking the Biden administration to prevent China from achieving dominance in Risc-V technology at the expense of U.S. national and economic security. Let’s now move to this week’s news roundup, starting with some EDA updates.
EDA updates: Cadence, Synopsys, Accellera
The new Cadence Voltus InsightAI is – according to the company – the industry’s first generative AI technology that automatically identifies the root cause of EM-IR drop violations early in the design process and selects and implements the most efficient fixes to improve power, performance, and area (PPA). As Cadence maintains, users of Voltus InsightAI can fix up to 95% of violations prior to signoff, leading to a 2X productivity improvement in EM-IR closure.
The new Synopsys Cloud OpenLink program enables chip designers to seamlessly access EDA tools and IP from multiple vendors in the Synopsys Cloud environment. As part of this initiative, the company is releasing an API specification that Synopsys Cloud OpenLink program members can use to deploy system-level integration with a secure and reliable transfer of entitlements to Synopsys Cloud.
Accellera has announced the availability of the Clock Domain Crossing (CDC) Draft Standard 0.1 for public review. This standard aims to ease SOC integration, which often involves combining in-house and externally purchased IPs. The public review is open through December 31, 2023.
