Intel Innovation event; Zuken’s AI-powered PCB tool; MEMS-based timing

Will Silicon Valley’s disruptive innovation capabilities extend to car body manufacturing? In addition to pioneering the use of huge presses with 6,000 to 9,000 tons of clamping pressure, Tesla is reportedly exploring other new solutions to slash the cost of electric vehicles. Technologies being investigated include 3D printing, industrial sand, tailor-made alloys. According to the report, Musk’s goal is to find a way to cast the car’s underbody in one piece.

EDA and IP updates: Zuken, Altair, Ultra Librarian, Intel

Zuken has introduced a three-stage approach to AI-powered PCB design within its CR-8000 platform. The Autonomous Intelligent Place and Route product line introduces a new platform for AI-based place and route, which evolves in stages. “Basic Brain” learns from Zuken’s library of design examples and existing design expertise, and routes the design utilizing the product’s Smart Autorouter based on learned approaches and strategies. In the second stage, Zuken’s “Dynamic Brain” learns from the customer’s PCB designers, utilizing past design examples and integrating them into AI algorithms. The third and final stage is the “Autonomous Brain”, an AI-driven capability that self-improves with each project.

The Ultra Librarian CAD model library is now available to Altair users in several Altair ECAD verification and multiphysics solutions, including PollEx, SimLab, and Altair One UDE. Ultra Librarian gives users instant access to more than 16 million symbols, footprints from a cloud-based library.

And Ultra Librarian has developed a new AI-driven CAD modeling engine to drastically reduce the time it takes to build CAD models.

Intel is launching a new soft processor in the Nios V family targeting its FPGAs: the Nios V/c compact microcontroller – a free, soft-core IP, based on the Risc-V architecture. It will initially target all devices supported in Intel Quartus Prime Pro software with a roadmap to many devices supported in Quartus Prime Standard software.

Intel innovation event

At the recent Intel Innovation event, CEO Pat Gelsinger said Intel’s “five-nodes-in-four-years” process development program is progressing well, with Intel 7 already in high-volume manufacturing, Intel 4 manufacturing-ready and Intel 3 on track for the end of this year. Gelsinger also showed an Intel 20A wafer with the first test chips for Intel’s Arrow Lake processor, which is destined for the client computing market in 2024. Intel 20A will be the first process node to include PowerVia, Intel’s backside power delivery technology, and the new gate-all-around transistor design called RibbonFET. Intel 18A, which also leverages PowerVia and RibbonFET, remains on track to be manufacturing-ready in the second half of 2024. Among the other innovations introduced at the event, one of the industry’s first glass substrates for next-generation advanced packaging, planned for the latter part of this decade. Intel also displayed a test chip package built with UCIe, combining an Intel UCIe IP chiplet fabricated on Intel 3 and a Synopsys UCIe IP chiplet fabricated on TSMC N3E process node. The chiplets are connected using embedded multi-die interconnect bridge (EMIB) packaging technology. As for personal computers, Gelsinger pitched the “AI PC” concept, set to arrive with the upcoming Intel Core Ultra processors, code-named Meteor Lake, featuring Intel’s first integrated neural processing unit. Othe notable announcements include plans to develop an ASIC accelerator for fully homomorphic encryption and related software.

Panmnesia funding

Companies developing CXL solutions – and addressing the ‘memory wall’ problem in datacenters – keep attracting investors. South Korea-based Panmnesia has recently completed a seed funding round totaling $12.5 million, bringing the company’s valuation to $81.4 million. Born out of a group of Ph.D. graduates from the Korea Advanced Institute of Science and Technology (KAIST), Panmnesia has recently disclosed a full system – from devices to operating systems – connected through a multi-level switch architecture supporting CXL 3.0.

AI chips update: Ampere, Sambanova

Ampere’s latest AmpereOne processor will be used by Oracle Cloud for its next generation Ampere A2 Compute Instances, with availability starting later this year. According to Oracle, the new instances will deliver up to 44% more price-performance compared to x86 offerings and are ideal for AI inference, databases, web services, media transcoding workloads and run-time language support, such as GO and Java.

SambaNova Systems has announced a new chip, the SN40L, which will power the company’s full stack large language model (LLM) platform, the SambaNova Suite. According to the company, the new chip on the inside offers both dense and sparse compute, and includes both large and fast memory. The SN40L, manufactured by TSMC, can serve a 5 trillion parameter model, with 256k+ sequence length possible on a single system node.

SiTime’s MEMS-based timing platform

SiTime’s Epoch Platform is a MEMS-based, oven-controlled oscillator (OCXO) that delivers an ultra-stable clock to datacenter and network infrastructure equipment, challenging conventional quartz-based timing platforms. According to the company, legacy quartz OCXOs are inherently unreliable and prone to performance degradation in the presence of environmental stressors such as temperature changes and vibration; they also offer less than ideal performance in terms of size, power, and warm-up time. In contrast, SiTime claims that the Epoch Platform delivers 2X longer holdover, even under environmental stressors, enabling telecom and cloud service providers to deliver service continuity in real-world conditions. Other claimed benefits include 3X lower power, 3X better ADEV (Allan deviation) under airflow, 3X lower aging, 2X faster time to stability, 9X smaller size.

Acquisitions

Cadence will acquire Intrinsix, a wholly owned subsidiary of CEVA and a provider of design engineering solutions focused on the U.S. aerospace and defense industry. The purchase will bring Cadence a highly skilled engineering team that has expertise in advanced nodes, radio frequency, mixed-signal and security algorithms.

Toshiba has reportedly said that a $14 billion tender offer from private equity firm Japan Industrial Partners (JIP) had ended in success – a deal which paves the way for the Japanese industrial conglomerate to go private. JIP’s consortium includes twenty Japanese companies, led by chipmaker Rohm.

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