Artificial intelligence, Moore’s law, chiplets, and High NA EUV were among the themes discussed by keynoters and panelists at the two industry events, both held in San Francisco from July 9-10 to July 13

Thousands of industry professionals and academic researchers involved in all different aspects of the semiconductor ecosystem gathered in San Francisco last week – either as attendees, exhibitors, presenters, or speakers – for the 2023 editions of the Design Automation Conference and Semicon West. Back to normal after the pandemic, the two co-located events offered a rich menu to the semiconductor community – combining research papers, exhibition floors, keynotes and panels. Adding to this offering, Semicon West was also co-located with the Flex event, and two European semiconductor research institutes – Belgium’s imec and France’s CEA-Leti – also organized their own forums at venues nearby (ITF Semicon USA and Leti Semicon Workshop, respectively). Here we will try to summarize some of the concepts that emerged from some of the keynotes and panels.

EDA: no disruptions ahead

Let’s start with EDA. Overall, it looks like the industry is not expecting any major disruptions on the short term. Artificial intelligence will obviously continue to play a key role in the evolution of EDA tools, but today this can be taken for granted and cannot be considered a new trend anymore. Part of the debate about EDA concerned the adaptation of existing EDA tools to the change of external conditions, such as the advent of cloud computing. The lack of disruptive innovations was effectively summarized by a rather provocative questions asked by Prit Banerjee, Ansys’ CTO, to EDA veterans Joe Costello and Wally Rhines during a panel. In short, Banerjee – speaking from the audience, not as a panelist – maintained that until now the major EDA vendors have just “tweaked” their EDA tools to adapt them to new technologies – such as parallel processing, AI, cloud computing – and asked if there is now space for a new EDA flow that is natively optimized for those new resources. Joe Costello answered that it’s a great idea, but today it would be difficult to find the money to undertake such an effort.

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Reportedly, the latest update on the U.S.-China tech fight is China’s decision to place exports restriction on gallium and germanium, which – according to some observers – could be followed by restrictions on rare earth exports. As for semiconductor subsidies updates, Broadcom will reportedly invest in a European Union-funded program in Spain which would include the construction of “large-scale back-end semiconductors facilities unique in Europe.” And French research institute CEA will receive funding from the French government for the construction of a new fab in Grenoble with the goal of downscaling FD-SOI (fully depleted silicon on insulator) chips below 10-nanometer and a to develop a new generation non-volatile onboard memory.

Samsung Foundry roadmap updates

On occasion of its recent Samsung Foundry Forum in San Jose, the South Korean company announced it will begin mass production of the 2-nanometer process for mobile applications in 2025, and then expand to HPC in 2026 and automotive in 2027. Mass production of SF1.4 will begin in 2027 as planned. From 2025, Samsung will begin foundry services for 8-inch gallium nitride power semiconductors. The 5-nanometer radio frequency process is also under development and will be available in the first half of 2025. Samsung Foundry is adding new manufacturing lines in Pyeongtaek, South Korea, and Taylor, Texas. The company said the construction of the new fab in Taylor is proceeding according to initial plans and is expected to finish by the end of the year, beginning operation in the second half of 2024. Among other news, Samsung is launching its ‘Multi-Die Integration Alliance’ in collaboration with partner companies and players in memory, substrate packaging, and testing. The MDI Alliance aims to create a packaging technology ecosystem for 2.5D and 3D heterogeneous integration.

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