Digitally wrapped analog IP; 3D DRAM; CHIPS Act and EDA; Python acceleration

Arm has officially started the process that will lead to its IPO on Nasdaq. As stated in a press release, the size and price range for the proposed offering have yet to be determined. Let’s now move to the rest of our weekly news roundup.

Market numbers: semiconductors 1Q2023, EDA 4Q2022

The chip market is slowing down. According to the Semiconductor Industry Association (SIA), worldwide sales of semiconductors totaled $119.5 billion during the first quarter of 2023, a decrease of 8.7% compared to the fourth quarter of 2022 and 21.3% less than the first quarter of 2022. Sales for the month of March 2023, however, increased 0.3% compared to February 2023. The EDA market, in contrast, is doing well. As recently announced by the ESD Alliance, Electronic System Design industry revenue increased 11.3% from $3,468.2 million in the fourth quarter of 2021 to $3,858.7 million in the fourth quarter of 2022.

Smartphone chipmakers seeking diversification

In terms of chip demand, one of the market segments that are suffering is smartphones, and this is having an impact on the leading smartphone chip suppliers. Qualcomm’s shares reportedly sank 7%, over the past few days, after the company signalled it would take longer for the smartphone market to rebound from a post-pandemic slump. Qualcomm, however, is diversifying towards automotive and IoT application, and its automotive revenue grew 20% from Q2 2022 to Q2 2023. A similar diversification strategy is being pursued by MediaTek: “We are definitely moving our resources very, very rapidly toward the automotive and computing area because those areas will provide our growth in the next three to five years in the future,” said MediaTek’s CEO Rick Tsai during the 1Q23 earnings call.

Digitally wrapped analog subsystems

Agile Analog has launched its first range of “digitally wrapped” analog subsystem IPs – that is, blocks of analog IP surrounded by the digital circuitry which is necessary to connect them with the rest of a digital ASIC via a standard peripheral bus, such as AMBA APB. The initial range includes a power management subsystem, a PVT (process, voltage and temperature) sensor subsystem, and a sleep management subsystem. According to the company, these digitally wrapped subsystems significantly reduce the effort required to integrate multiple analog IPs into any ASIC by allowing the IP to be dropped straight into a digital design flow, since they look just like a normal block of digital IP with the standard interfaces that engineers would expect. This saves users from dealing with the complex mixed-signal boundary between analog and digital, decreasing their design effort. Additional benefits claimed by the company include increased noise immunity, lower power consumption, smaller area, and a reduction of verification time since the verification requirements of the analog to digital, mixed-signal, boundary are performed by Agile Analog. The digitally wrapped analog IP subsystems are customizable and process/foundry agnostic.

New 3D DRAM architecture can be manufactured with 3D NAND-like process

San Jose-headquartered NEO Semiconductor has launched what it claims is the world’s first 3D DRAM based on an architecture similar to 3D NAND Flash memory. Dubbed 3D X-DRAM, the new memory employs a cell array structure based on capacitor-less floating body cell technology. According to the company, it can be manufactured using today’s 3D NAND-like process and only needs one mask to define the bit line holes and form the cell structure inside the holes. This cell structure simplifies the process steps and provides a high-speed, high-density, low-cost, and high-yield solution. Based on Neo’s estimates, 3D X-DRAM technology can achieve 128 Gb density with 230 layers, which is eight times today’s DRAM density.

CHIPS Act and EDA: IP sharing, design portability, dataset collection, benchmarking

The National Institute of Standards and Technology (NIST) has released a paper outlining its vision and strategy for a National Semiconductor Technology Center (NSTC), a key component of the research and development program established by U.S. “CHIPS and Science Act”. The document also addresses EDA and IP, envisioning initiatives that – if realized – could have an impact on the status quo. NIST envisions a “cloud-based, design enablement gateway” aimed at ensuring “that IP can be safely shared” within semiconductor fabless R&D. Another “priority of NSTC-based research and funding into EDA and circuit design could be aimed at increasing the portability of designs between foundries and technology nodes. Research into this area could reduce the time it takes to spin up new processes at foundries as well as improve the ability to rapidly qualify ported designs.” Additionally, “The Department envisions a role for the NSTC in collecting, aggregating, and sharing data sets that enable benchmarking and operational improvements, tools development, the creation of digital twins, and training AI models.” The paper includes a summary of the input provided by the semiconductor community as for the requirements for a new hosted design environment.

UMC’s 40nm RFSOI process ready for production

Taiwanese foundry UMC has announced that its 40-nanometer RFSOI technology platform is now ready for production of millimeter-wave radio frequency front-end products, targeting 5G wireless networks and other applications.

New memory allocation technology promises a 10x software acceleration

Fabless startup VyperCore, based in the UK, is developing a modified Risc-V processor which will incorporate its novel hardware memory allocation management technology. According to the company, this fundamental remodelling of hardware memory interfaces enables to accelerate software written in modern languages, such as Python and C#, by up to a factor of 10. VyperCore also claims it can even achieve a >1.5x speedup on software written in older languages like C and C++. Initially the company is focusing on application software (as opposed to low-level system software) where the new technology maintains source code compatibility across languages (from Python to C/C++.) This will enable deployment of the VyperCore accelerator card in data centers without developers needing to change their programs. Additionally, the company claims that its memory management technology can eliminate the most prominent memory safety issues, such as buffer overflows and use-after-free, without sacrificing performance, silicon area or power.

SiC updates: Infineon deals, Wolfspeed-ZF R&D center

Germany-headquartered Infineon is diversifying its silicon carbide supplier base through agreements with Chinese suppliers TanKeBlue and SICC. Both companies will supply Infineon with 150-millimeter SiC wafers and boules for the manufacturing of SiC semiconductors. Not far away from Infineon headquarters, in the Nuremberg Metropolitan Region, ZF and Wolfspeed plan to establish a joint European R&D center for silicon carbide power electronics.

This entry was posted on Friday, May 5th, 2023 at 10:51 am. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.