Archive for November, 2022
Saturday, November 26th, 2022
This year’s fall edition of the Linley Processor Conference – held on November 1 and 2 in Santa Clara, California – was, as usual, a good observation point to keep abreast of trends and products in neural network acceleration. In this article we will provide a very quick overview of part of the conference, focusing on the keynote given by Linley Gwennap and on the presentations from the companies that addressed AI acceleration topics. The event, of course, offered many more presentations concerning ‘conventional’ (non-AI) processors and other processing-related themes, which we will not cover here.
Linley Gwennap’s keynote: trends in AI acceleration
In his keynote, Linley Gwennap – principal analyst at TechInsights – noted that the growth of AI model size has slowed, as training has become increasingly resource-intensive: for example, training the GPT-3 language processing model takes 1,024 Nvidia A100 GPUs over one month. Rapid growth of AI model size has been enabled by moving training to large processing clusters, but cluster size is topping out for cost reasons: 1,024 GPUs cost approximately $25 million. As a result, essentially there has been no growth in largest trained models over the past year, and recent progress focuses on models with less compute per parameter. Future growth of AI model size will be paced by hardware progress, e.g. the availability of new Nvidia H100 clusters.
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Friday, November 18th, 2022
Geopolitical tensions keep making headlines, with Japan trying to catch up on advanced nodes capabilities to gain more independence from foreign suppliers. Western world investments in new fabs continue, with Infineon planning for the construction of a factory for 300-millimeter analog/mixed-signal and power semiconductors in Dresden, Germany. More news this week include three interesting academic research works.
Japanese government to subsidize a new domestic chipmaker
As reported by The Japan Times, eight major Japanese companies have jointly invested to launch a new firm, named Rapidus, tasked with developing 2-nanometer chips by 2027, in collaboration with IBM. The eight companies – Toyota, Sony, NTT, SoftBank, Kioxia, Denso, NEC and MUFG Bank – invested a total of ¥7.3 billion ($52 million) to form the new venture, which is chaired by Tetsuro Higashi, former president of chip equipment firm Tokyo Electron. The Japanese government plans to provide the new company with ¥70 billion ($500 million) in subsidies, backed by a second extra budget. Japan will also create a new body for chip research and development called ‘Leading-edge Semiconductor Technology Center’ (LSTC) by the year’s end, consisting of Japan’s major research bodies and universities. Reportedly, analysts are skeptical about the success of Rapidus, as the financial support promised by the Japanese government so far is much smaller than the amounts set out by the U.S. and the European Union for their ‘chips acts’, $52.7 billion and €43 billion ($45 billion) respectively.
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Monday, November 14th, 2022
A closer look at the recently announced ‘Joint Enterprise Data and AI’ infrastructure, an AI-driven, big data analytics environment
Announced last September 13, the JedAI platform is the new Cadence AI-driven, big data analytics environment, meant to be tightly integrated with the company’s recently introduced AI-based platforms: Verisium for verification, Cerebrus for implementation, and Optimality for system optimization. Features and benefits of JedAI were described by Rod Metcalfe – Product Management Group Director, Digital and Signoff Group at Cadence – in the video interview he recently gave to EDACafe’s Sanjay Gangal; building on that interview, in this article we will add a few more details with the help of a Cadence white paper – along with the answers provided by Rod and by Kam Kittrell – vice president, Product Management in the Digital & Signoff Group at Cadence – to some additional questions.
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Friday, November 4th, 2022
Taiwanese foundry TSMC and its collaboration with major EDA partners make up a large part of this week’s news roundup. Other foundries are in the news as well. But first, a quick look at some market data and investment trends.
EDA record revenues
Record numbers are being reported for the Electronic System Design industry: as announced by the ESD Alliance, revenue increased 17.5% from $3,191.4 million in Q2 2021 to $3,748.7 million in Q2 2022. The four-quarter moving average, which compares the most recent four quarters to the prior four, rose 15.3%. As noted by Wally Rhines, the EDA industry in Q2 2022 posted the highest year-over-year increase in over a decade, and all product categories and geographic regions recorded growth in the quarter.
Fab capex reduction
Several chipmakers, however, are cutting their planned capital expenditure citing weaker consumer demand. Among them Taiwanese foundry UMC, which will reportedly reduce its capex by almost a fifth, and South Korean memory maker SK hynix, which has decided to cut its investment next year by more than 50% YoY, citing an unprecedented deterioration of the market conditions in the semiconductor memory industry as uncertainties in the business environment continue.
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Tuesday, November 1st, 2022
Thanks to real-time integration with the physical design flow and to new optimization algorithms, the solution promises dramatic TAT improvements and significant PPA benefits for large SoCs and multi-die designs – running on single box hardware
Major EDA vendors are launching new products to address the challenges of design closure and ECOs in deep-submicron SoCs. On October 5th Synopsys introduced its new PrimeClosure solution. Jacob Avidan, senior vice president of Engineering for the Silicon Realization Group at Synopsys, described the features of PrimeClosure in the video interview he recently gave to EDACafe’s Sanjay Gangal. Building on that interview, in this article we will add some more details about the new solution by means of the answers that Manoj Chacko, Director of Product Marketing for Synopsys PrimeClosure, provided to our additional questions.
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