Based on a parallel architecture and a ‘distributed optimization engine’, the new automated environment builds on Cadence’s implementation system (Innovus) and timing signoff solution (Tempus), and promises up to 10X faster closure for designs greater than ten million cells
With SoCs targeted at advanced applications getting ever larger and complex, moving from block-level optimization to full-chip design closure has become a challenging and time-consuming task for design teams. The current, manual full-chip closure flow involves many steps and iterations – from assembly, static timing analysis, and optimization and signoff with hundreds of views. According to Cadence, today’s design teams often spend five to seven days per iteration to meet chip-level signoff timing and power requirements, therefore this error-prone process can take designers months to converge.
Additionally, current methodologies are considered inefficient in terms of team collaboration and user experience. Addressing these problems, Cadence has recently launched Certus Closure Solution, an environment aimed at accelerating full-chip design closure by means of a parallel architecture and automation of previously manual tasks. Brandon Bautz – Senior Group Director of Product Management, responsible for the Cadence silicon signoff and verification product lines in the Digital & Signoff Group at Cadence – described the features of Certus in the video interview he recently gave to EDACafe’s Sanjay Gangal. In this article we will add some more details about Certus, building on that video interview and on the answers Bautz provided to our additional questions.
