The new Cerebrus Intelligent Chip Explorer recently announced by Cadence is a machine learning-based tool that automates and scales digital chip design, in combination with the Cadence RTL-to-signoff flow. It promises the ability to improve engineering productivity by up to 10X versus a manual approach while also realizing up to a 20% better power, performance and area (PPA) metrics. Rod Metcalfe, Product Management Group Director at Cadence Design Systems, has described the key features of Cerebrus in the video interview he has recently given to EDACafe’s Sanjay Gangal; in addition to that, we have asked Rod a few more questions on some specific aspects of the tool.
Key ingredients: reinforcement learning, distributed computing
As Metacalfe explained in the video interview, Cadence thinks Cerebrus will represents the future of digital chip design. “First of all – he said – we’ve developed a unique reinforcement machine learning engine that really helps optimize the full flow of a digital design. This will allow chip designers to get better PPA more quickly, so it’s going to improve the productivity of the design teams. Now, this is an automated RTL to GDS full flow optimization, and it’s based on some distributed computing technology. It can either be on-premises compute or it can be cloud resources, but the idea is really that Cerebrus is very scalable. It can adapt to the bigger designs that design teams are doing today.”
