Not just lithography: scaling to 2-nanometers and beyond involves many difficult manufacturing challenges. A virtual event and a series of blog posts from Applied Materials help understand how these problems can be solved with coordinated solutions based on new transistor architectures, new materials, new manufacturing processes
Over the past few years, the transition to EUV lithography has received a lot of attention as a key enabling technology for further IC scaling. But moving to the next advanced process nodes is not just about projecting smaller patterns; in fact, the resulting size reduction of every circuit feature opens a set of new, complex problems that need to be addressed in order to achieve the expected PPA benefits. Let’s take a look at these challenges with the help of Applied Material’s experts. In a ‘Logic Master Class’ held as a virtual event last June 16th – still available on demand – and in a series of related blog posts, Mike Chudzik, Mehul Naik and Regina Freed addressed different aspects of the scaling of logic ICs, stressing the increasing importance of ‘design-technology co-optimization’ (DTCO). Applied Materials describes DTCO as a way to “reduce area-cost without changing the lithography and pitch,” using a combination of architectures, processes and materials. In this quick overview of the class, we will only summarize some of the general concepts.
Pitch scaling is not enough
The need for innovation stems from the fact that just building a smaller version of the same device – as in the traditional method, called pitch scaling or ‘intrinsic scaling’ – would lead to bad power and performance results and to increased device variability. This is because size reduction generates new limiting factors. Trying to generalize, one could say that there are mechanical limitations, electrical limitations, and process limitations. Mechanical limitations include the fact that some elements may become too weak to withstand mechanical stress; electrical limitations mostly refer to the increased resistance of current paths – signal or power – due to smaller cross section area; and process limitations include the fact that certain specific elements – e.g. certain material layers – cannot scale proportionally, or that patterning inaccuracy become a larger percentage of the intended feature. Collectively, these limitations are now determining the transition from FinFET to GAA (Gate-All-Around) transistors.
