Open side-bar Menu
 EDACafe Editorial

Archive for August, 2021

Intel process and architecture updates; AI in EDA attracting investors; Foxconn to add SiC and MEMS offering

Friday, August 27th, 2021

Catching up on some of the news from the last four weeks or so, Intel stands out with its late-July and mid-August announcements which we will briefly recall below – along with several more news from various areas. But first, a quick update on the Nvidia-Arm deal: according to the UK Government’s Competition and Markets Authority (CMA), this acquisition would “lead to a realistic prospect of a substantial lessening of competition”. Another quick update about GlobalFoundries, which – according to Reuters – has filed confidentially with U.S regulators for an initial public offering (IPO) in New York.

EDA updates: Cadence, Motivo, Avishtech

Anirudh Devgan to become Cadence CEO. Current Cadence CEO Lip-Bu Tan will transition to the role of executive chairman on December 15, 2021, with President Anirudh Devgan assuming the role of president and CEO at that time. Devgan has also joined the Cadence Board of Directors.

AI-enabled EDA tools developer Motivo raises $12 million financing. The Series A financing round is led by Intel Capital and follows earlier seed rounds of $8 million. Motivo’s technologies accelerate chip design utilizing a “learning-on-graph” methodology for automated data-driven feature extraction. According to the company, Motivo’s M-Graph and other explainable AI technologies can be applied across the entire design flow, from RTL code to layout geometries. With this approach, Motivo aims to compress the design-to-manufacturing process from years to months.

(more…)

Machine Learning-Based Cerebrus for Intelligent Chip Design

Friday, August 6th, 2021

The new Cerebrus Intelligent Chip Explorer recently announced by Cadence is a machine learning-based tool that automates and scales digital chip design, in combination with the Cadence RTL-to-signoff flow. It promises the ability to improve engineering productivity by up to 10X versus a manual approach while also realizing up to a 20% better power, performance and area (PPA) metrics. Rod Metcalfe, Product Management Group Director at Cadence Design Systems, has described the key features of Cerebrus in the video interview he has recently given to EDACafe’s Sanjay Gangal; in addition to that, we have asked Rod a few more questions on some specific aspects of the tool.

Key ingredients: reinforcement learning, distributed computing

As Metacalfe explained in the video interview, Cadence thinks Cerebrus will represents the future of digital chip design. “First of all – he said – we’ve developed a unique reinforcement machine learning engine that really helps optimize the full flow of a digital design. This will allow chip designers to get better PPA more quickly, so it’s going to improve the productivity of the design teams. Now, this is an automated RTL to GDS full flow optimization, and it’s based on some distributed computing technology. It can either be on-premises compute or it can be cloud resources, but the idea is really that Cerebrus is very scalable. It can adapt to the bigger designs that design teams are doing today.”

(more…)

Verific: SystemVerilog & VHDL Parsers
True Circuits DDR PHY



© 2022 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise