Quarterly result announcements – either from Q1 or Q2 – make up a significant part of this week’s news roundup. Manufacturing capacity expansion continues to be a hot topic, but there is no shortage of other updates. Quantum computing research is also in the news with two announcements.

Record EDA and IP revenues in Q1 2021

According to the latest report from the ESD Alliance, in Q1 2021 the Electronic System Design industry revenue increased 17% to $3,157.17 million, marking the strongest first-quarter growth ever. The four-quarter moving average, which compares the most recent four quarters to the prior four, rose 15%, the highest annual growth since 2011. All product categories significantly contributed, with double-digit growth in the CAE, IC physical design/verification, PCB/MCM, and semiconductor IP segments. Geographically, the Americas, EMEA and APAC regions also reported double-digit growth. Outstanding figures have been achieved by IC physical design and verification revenue, which surged 34.4% to $682.5 million compared to Q1 2020; and by the Asia Pacific revenue, which increased 26.9% to $1,166.3 million compared to Q1 2020. Quoted by Semiconductor Engineering, Wally Rhines – executive sponsor of SEMI‘s Electronic Design Market Data Report – underlined the Chinese figures: “Year on year, the revenue in China was up 73%. And if you look at EDA only, separate from IP, it was up 99%,” he reportedly said.

EDA updates: Ansys cloud support, Julia Computing funding

In collaboration with Arm, Ansys is enabling simulation solutions for AWS Graviton2 processors, a more affordable way to access Amazon Web Services cloud computing resources. The initiative marks the first availability of Ansys’ semiconductor simulation solutions on the Arm Neoverse architecture. Beginning with the APL (Ansys Power Library) characterization tool, Ansys will offer more of its semiconductor analysis software product suite, supporting the Arm Neoverse architecture that is used by AWS Graviton2-powered Amazon Elastic Compute Cloud instances.

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Investments – both announced and rumored – make up a significant part of this week’s news roundup. More updates concern automotive applications and AI chips.

Intel reportedly in talks to buy GlobalFoundries

According to the Wall Street Journal, Intel is exploring a deal to buy GlobalFoundries, in a move that would represent its largest acquisition ever. A deal could value GlobalFoundries at around $30 billion, sources said. It isn’t guaranteed that the acquisition will take place; alternatively, GloFo could proceed with a planned initial public offering. GlobalFoundries is owned by Mubadala Investment Co., an investment arm of the Abu Dhabi government. As noted by WSJ, AMD remains a big customer for GlobalFoundries, and that could complicate a takeover by Intel.

Rohm to invest in semiconductor startups

Japanese chipmaker Rohm has reportedly launched a 5 billion yen ($45.3 million) venture capital fund to invest in next-generation semiconductor technology. Among first beneficiaries is US startup Locix, a developer of cloud-based spatial intelligence solutions for commercial buildings, consumer homes and connected devices. Locix solutions capture location, visual and sensor data and combine them with data analytics to provide spatial awareness.  Based in San Bruno, CA, Locix is backed by several other Japanese investors, too.

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Not surprisingly, several news this week are somewhat related to fabs and foundries – in terms of customer contracts, new fabs, acquisitions, equipment – as companies around the world are repositioning to take advantage of the semiconductor boom. Another interesting update concerns Simon Segars speaking about the Nvidia deal. More news is coming from the International Supercomputing Conference and from the latest MLPerf results.

Apple and Intel reportedly first to adopt TSMC’s 3 nm process

According to Nikkei Asia, Apple and Intel have emerged as the first adopters of TSMC’s 3-nanometer process ahead of its deployment as early as next year. Commercial output of such chips is expected to start in the second half of next year. Apple’s iPad will likely be the first devices powered by processors made using 3-nanometer technology. Intel is reportedly working with TSMC on at least two 3-nanometer projects concerning CPUs for notebooks and data center servers. Mass production of these chips is expected to begin by the end of 2022 at the earliest. Reportedly, the chip volume planned for Intel is more than that for Apple’s iPad.

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Not just lithography: scaling to 2-nanometers and beyond involves many difficult manufacturing challenges. A virtual event and a series of blog posts from Applied Materials help understand how these problems can be solved with coordinated solutions based on new transistor architectures, new materials, new manufacturing processes

Over the past few years, the transition to EUV lithography has received a lot of attention as a key enabling technology for further IC scaling. But moving to the next advanced process nodes is not just about projecting smaller patterns; in fact, the resulting size reduction of every circuit feature opens a set of new, complex problems that need to be addressed in order to achieve the expected PPA benefits. Let’s take a look at these challenges with the help of Applied Material’s experts. In a ‘Logic Master Class’ held as a virtual event last June 16^th – still available on demand – and in a series of related blog posts, Mike Chudzik, Mehul Naik and Regina Freed addressed different aspects of the scaling of logic ICs, stressing the increasing importance of ‘design-technology co-optimization’ (DTCO). Applied Materials describes DTCO as a way to “reduce area-cost without changing the lithography and pitch,” using a combination of architectures, processes and materials. In this quick overview of the class, we will only summarize some of the general concepts.

Pitch scaling is not enough

The need for innovation stems from the fact that just building a smaller version of the same device – as in the traditional method, called pitch scaling or ‘intrinsic scaling’ – would lead to bad power and performance results and to increased device variability. This is because size reduction generates new limiting factors. Trying to generalize, one could say that there are mechanical limitations, electrical limitations, and process limitations. Mechanical limitations include the fact that some elements may become too weak to withstand mechanical stress; electrical limitations mostly refer to the increased resistance of current paths – signal or power – due to smaller cross section area; and process limitations include the fact that certain specific elements – e.g. certain material layers – cannot scale proportionally, or that patterning inaccuracy become a larger percentage of the intended feature. Collectively, these limitations are now determining the transition from FinFET to GAA (Gate-All-Around) transistors.

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