According to industry association SEMI, semiconductor manufacturers around the world will start the construction of nineteen new high-volume fabs by the end of this year, and ten more fabs will be added in 2022. So it’s no surprise that several announcements this week concern new fabs. Besides rumors about a new European site, Intel is in the news also for its organizational changes that – to some extent – reflect the growing importance of AI and hyperscale data centers. Among other news is a further advancement of machine learning in EDA-related technologies, namely FPGA design tools; and a new manufacturing process enabling further scaling.
Intel reportedly in talks on a new fab near Munich, Germany
Intel is reportedly in talks with the German state of Bavaria to build a new fab, with the goal of countering the chip shortage that is damaging the automotive industry. According to the report, in recent months Intel has been seeking 8 billion euros (US$9.5 billion) in public subsidies to build a semiconductor manufacturing site in Europe. Reportedly, the Bavarian Economy Minister is strongly supporting the initiative. The Bavarian government has suggested a disused air base in Penzing-Landsberg, west of Munich, as a possible location for the factory. The German state of Bavaria is home to carmaker BMW, and the Munich area is a significant semiconductor manufacturing hub, hosting – among others – a large Texas Instruments factory.
Acquisitions stand out in this week’s news roundup, catching up on some of the updates from the last fifteen days or so. But first, some interesting news about the evolution of the processor industry landscape, the use of deep learning in chip design, and foundry roadmaps.
Intel reportedly considering SiFive acquisition
The Nvidia-Arm deal – still under regulatory scrutiny – and the recent appointment of Pat Gelsinger as new Intel CEO are two factors that keep shaking the processor industry. Intel is reportedly considering the acquisition of SiFive, in a move that would enable the Santa Clara giant to add a rich portfolio of Risc-V-based IP, an open-source alternative to Arm. As noted in another report, with the acquisition Intel would also gain a software boost thanks to SiFive experts such as Chris Lattner. Meanwhile, concerns about the Nvidia-Arm deal start to emerge publicly. Qualcomm President Cristiano Amon has reportedly said that – in case SoftBank decides to launch an IPO for Arm – his company and many others would be interested in buying a stake.
Cristiano Amon. Credit: Qualcomm
Google’s research work on deep learning-based chip floorplanning: updates
Preceded in April 2020 by a preprint posted on the online arXiv repository, the paper from Azalia Mirhoseini and other Google researchers about deep learning- based chip floorplanning has recently been published by Nature magazine – with the addition of methods that improve results and that have been used in production to design the next generation of Google TPUs. One year after preprint, the topic cannot be considered ‘news’ anymore – but it’s definitely worth attention. Quoting from the paper abstract: “In under six hours, our method automatically generates chip floorplans that are superior or comparable to those produced by humans in all key metrics, including power consumption, performance and chip area.
The importance of a holistic system-level approach was one of the common themes across the keynotes speeches given by top executives and guests at CadenceLIVE Americas 2021, a virtual event held on June 8 and 9. Machine learning, of course, was a major topic too – both in terms of new product announcements and R&D directions.
The ‘semiconductor renaissance’ and the role of hyperscalers
Cadence CEO Lip-Bu Tan opened the event by discussing the theme of ‘semiconductor renaissance’, the current silicon boom fueled by 5G, autonomous vehicles, industrial IoT, AI/ML. “It’s the first time we have multiple strong drivers at the same time,” he noted. “A few years ago, people were thinking semiconductor was a slowing, sunset industry, but not anymore. (…) We are currently facing a supply chain issue, but it’s due to overwhelming broad base demand. It is a great time to be in the semiconductor and electronics industry.” In his speech, Lip-Bu Tan devoted a special attention to the role of hyperscalers. “Hyperscalers are at the center of the renaissance and data revolutions,” he said. “Massive CAPEX spend, estimated at over 120 billion last year; over six hundred hyperscale data centers, with over a hundred opened in pandemic year 2020,” he pointed out. “[Hyperscalers[ participate in all stages of the data cycle and are pushing the need for innovation in technologies across computer, memory, storage and networking. (…) Hyperscalers are also pushing the most advanced process nodes, focus on the latest IP protocols (…). And they need advanced packaging, and also a lot of system-level simulation. It’s not just about chips to meet their needs; system level optimization across compute, networking and other hardware is needed, but also software needs to be co-optimized.” Among other things, Lip-Bu Tan also underlined the growth opportunities offered by data analysis and edge computing. Providing a general overview of all Cadence business, he also mentioned that Cadence Cloud is being used by over 175 customers.
New materials, new transistor structures, new integration schemes: many of the boost scaling options being investigated by research teams around the world will be represented at the 2021 Symposia on VLSI Technology & Circuits – running as a virtual event from June 13 to 19. Just as a teaser, in this article we will briefly summarize a handful of papers from the Technology program, to give a taste of some current research trends.
Benefits of forksheet over nanosheet
One of the papers presented by Belgian research institute Imec is meant to demonstrate the benefits of forksheet transistors over nanosheet transistors for CMOS area scaling. Forksheet devices are lateral nanosheet devices with a forked gate structure. The physical separation of N- and PFETs by a dielectric wall enables N-P space scaling and consequently sheet width maximization – compared to a N-P nanosheet configuration – for the same footprint. According to Imec, forksheet transistors offer additional benefits in the manufacturing process. Firstly, for nanosheets the high mask aspect ratio is challenging for patterning a well-defined N-P boundary over the full stack height. Secondly, the pWFM (Work Function Metal) lateral etch in-between NMOS nanosheets can lead to mask undercut and therefore pWFM removal from PFETs. For forksheet devices, the mask aspect ratio at the N-P boundary is substantially lower because the mask edge lands on top of the wall. In addition, the risk of pWFM removal from PFETs due to mask undercut is eliminated by the physical separation of the pWFM on either side of the wall, including along the gate trench side walls. Electrostatic control for forksheets and nanosheets is comparable.
Nanosheet (left) vs forksheet (right) comparison. Source: 2021 VLSI Symposia
