EDACafe Editorial Roberto Frazzoli
Roberto Frazzoli is a contributing editor to EDACafe. His interests as a technology journalist focus on the semiconductor ecosystem in all its aspects. Roberto started covering electronics in 1987. His weekly contribution to EDACafe started in early 2019. New emulation and prototyping systems; Arm v9 architecture; low power FPGAs; HKMG DRAM; automotive startups; open source updatesApril 8th, 2021 by Roberto Frazzoli
Google’s AI scientist Samy Bengio has reportedly resigned over a controversy with the company. Brother of Yoshua Bengio, another world-famous AI scientist, Samy joined Google in 2007 and was part of the TensorFlow team. Prior to that, Samy Bengio co-developed Torch, the ancestor of PyTorch. It will be interesting to see where he will be landing next. Let’s now move to some updates, catching up on some of the news from the last couple of weeks. Cadence Palladium Z2 and Protium X2 systems Cadence has introduced the Palladium Z2 Enterprise Emulation and Protium X2 Enterprise Prototyping systems, representing the new generation of the current Palladium Z1 and Protium X1. Based on new emulation processors and Xilinx UltraScale+ VU19P FPGAs, these systems provide – according to Cadence – 2X capacity and 1.5X performance improvements over their predecessors. Both platforms offer a modular compile technology capable of compiling 10 billion gates in under ten hours on the Palladium Z2 system and in under twenty-four hours on the Protium X2 system. Siemens’ new Veloce system Siemens has unveiled its new Veloce hardware-assisted verification system, that combines virtual platform, hardware emulation, and FPGA prototyping technologies. The solution includes four new products: Veloce HYCON (HYbrid CONfigurable) for virtual platform/software-enabled verification; Veloce Strato+, a capacity upgrade to the Veloce Strato hardware emulator that scales up to 15 billion gates; Veloce Primo for enterprise-level FPGA prototyping; and Veloce proFPGA for desktop FPGA prototyping. Customer-built virtual SoC models can begin running real-world firmware and software on Veloce Strato+ for deep-visibility to the lowest level of hardware, then the same design can be moved to Veloce Primo to validate the software/hardware interfaces and execute application-level software while running closer to actual system speeds. Both Veloce Strato+ and Veloce Primo use the same RTL, the same virtual verification environment, the same transactors and models. A key technology in the upgraded Veloce platform is a new, proprietary 2.5D chip which – according to Siemens – enables a 1.5x system capacity increase over the previous Strato system.
New Arm v9 design introduces the ‘Confidential Compute Architecture’ Arm has recently introduced Arm v9, its first new architecture in a decade, addressing the growing demand for specialized processing with increasingly capable security and artificial intelligence functions. A key innovation introduced by v9 is the Arm Confidential Compute Architecture (CCA). Confidential computing shields portions of code and data from access or modification while in-use, even from privileged software, by performing computation in a hardware-based secure environment. The Arm CCA will introduce the concept of dynamically created ‘Realms’, useable by all applications, in a region that is separate from both the secure and non-secure worlds. More innovations in Arm v9 include SVE2, a new version of the Scalable Vector Extension technology developed in collaboration with Fujitsu for the Fugaku supercomputer. The SVE2 in Arm v9 is expected to enable enhanced machine learning and digital signal processing capabilities across a wider range of applications. FPGA updates: Efinix, Lattice Efinix has expanded its Titanium FPGA product line to include devices up to 1M logic elements. According to Efinix, Titanium FPGAs offer significant PPA and cost advantages over traditional FPGA technologies, enabling them to challenge ASIC devices in high-volume, mainstream markets. Lattice has expanded its Crosslink-NX family with new FPGAs specified for automotive applications such as ADAS and in-vehicle infotainment systems. AEC-Q100 qualified up to Grade 2, the new CrossLink-NX FPGAs are built with a low-power FD-SOI process and support embedded MIPI D-PHY interfaces with speeds up to 10 Gbps. Memory updates: Samsung, Kioxia Samsung has developed what it claims to be the industry’s first 512GB DDR5 module based on High-K Metal Gate (HKMG) process technology. Moving to Flash memories, Micron Technology and Western Digital are reportedly exploring possible deals for Kioxia that could value the former Toshiba Memory at around $30 billion. An IPO later this year is still a possibility for Kioxia, according to the report. Silicon Valleys’ most valuable automotive startups Market research firm CB Insights has compiled a list of the ten most valuable private, venture capital-backed auto tech companies. Among the American ones, five are headquartered in Silicon Valley and one in San Francisco. These six companies are Aurora, based in Mountain View and valued $10B; Pony.ai, Fremont, $5.3B; Nuro, Mountain View, $5B; Quanergy, Sunnyvale, $2B; KeepTruckin, San Francisco, $1.3B; and Applied Intuition, Sunnyvale, $1.3B. Not all of these companies are directly involved in developing autonomous vehicles. Quanergy develops LiDAR products; KeepTruckin offers fleet management software and dashcams; Applied Intuition provides simulation software used in the development of autonomous vehicles. Open source updates: SkyWater, Tropic Square US foundry SkyWater Technology and crowdsourcing design platform Efabless have announced the first tapeout in a series of Google-sponsored open source multi-project wafer (MPW) shuttles. In this partnership, open source designs were selected to be fabricated at no cost to designers, using SkyWater’s 130nm process. The initiative used open source technologies to all levels, including design tools, IP, and foundry process design kits. Approximately 60% of the designs were submitted by “non-IC experts”, such as software, FPGA and hardware developers. Czech startup Tropic Square is developing what it claims to be “the first fully transparent and auditable security chip in the world.” According to the company, the traditional closed-source security chips prevent users from verifying the designs. Additionally, manufacturers of specialist security chips require their clients to sign NDA contracts, which makes it difficult to issue security risk alerts in case of problems. Initial applications of the Tropic Square chip are expected in the area of cryptocurrencies. Upcoming virtual events Above-mentioned Yoshua Bengio will be one of the keynote speakers at next Nvidia GTC, which will take place from April 12 to 16. Nvidia CEO Jensen Huang’s keynote is scheduled for April 12; more keynotes will be given by guests as famous as Facebook’s AI expert Yann LeCun. SEMI Industry Strategy Symposium Europe (ISS Europe) is scheduled for 20-22 April. Here is the agenda of the event. The former Mentor User2User conference, now a Siemens EDA event, will take place next May 26 in combination with Realize Live, a Siemens Digital Industries initiative. |