A quick look at DATE Conference 2021

DATE Conference 2021 was held as a virtual event from February 1^st to 5^th. As usual, it offered a wide selection of papers – mostly from academic researchers – on a range of topics including design automation, neural networks, automotive applications, quantum computing, security, cyber-physical systems etc. In this article we will briefly summarize just a few papers presented at the DATE 2021 – in no particular order – only to give a taste of the event. For each paper, only the speaker’s affiliation is indicated here, even though the works usually involved multiple universities or research institutions.

University of Stuttgart (Germany) discussed Negative Capacitance Field-Effect Transistors (NCFETs) as a new beyond-CMOS technology with advantages for offering low power and/or higher accuracy for neural network inference; and Ferroelectric FET (FeFET) as a novel non-volatile, area-efficient and ultra-low power memory device.

TU Dresden (Germany) addressed emerging ‘reconfigurable nanotechnologies’ that allow the implementation of self-dual functions with a fewer number of transistors as compared to traditional CMOS technologies. The team developed methods to achieve better area results for Reconfigurable Field-Effect Transistors (RFET)-based circuits.

Purdue University (USA) presented a first open source all-digital SerDes for multi-GHz serial links designed using Skywater OpenPDK 130nm process node. The physical design flow utilizes OpenLANE, which is an open source end-to-end tool for generating GDS from RTL. Cadence Virtuoso has been used for extracting parasitics for post-layout simulations, which exhibit the SerDes functionality at 2 Gbps for 34 dB channel loss while consuming 438 mW power.

The Chinese Academy of Sciences proposed a fully quantized version of BERT (FQ-BERT), including weights, activations, softmax, layer normalization, and all the intermediate results. Experiments demonstrate that the FQ-BERT can achieve 7.94× compression for weights with negligible performance loss. An accelerator tailored for the FQ-BERT based on Xilinx ZCU102 and ZCU111 FPGA achieves a performance-per-watt of 3.18 fps/W, which is 28.91× and 12.72× over Intel Core i7-8700 CPU and NVIDIA K80 GPU, respectively.

Sun Yat-sen University (China) presented a fast deep stereo-LiDAR fusion framework for real-time high-precision depth estimation. Called FastFusion, the solution provides an efficient two-stage fusion strategy that leverages binary neural network to integrate stereo-LiDAR information as input and use cross-based LiDAR trust aggregation to further fuse the sparse LiDAR measurements in the back-end of stereo matching.

ETH Zurich (Switzerland) addressed the problem of microarchitectural timing channels that use variations in the timing of events, resulting from competition for limited hardware resources, to leak information in violation of the operating system’s security policy. Such channels also exist on a simple in-order RISC-V core. The paper shows that adding a single flush instruction is sufficient to close all channels at negligible hardware costs, while requiring only minor modifications to the software stack.

Vienna University of Technology (Austria) made the first attempt to study the aging in the on-chip weight memories of deep neural network hardware accelerators, caused by Negative Biased Temperature Instability. The team proposed a specialized aging-mitigation framework for DNNs, which jointly exploits hardware- and software-level knowledge to improve the lifetime of the DNN weight memory with reduced energy overhead.

Brown University (USA) formulated the problem of migrating EDA jobs to the cloud. First, the team characterized the performance of four main EDA applications, namely: synthesis, placement, routing and static timing analysis. They showed that different EDA jobs require different machine configurations. Second, they proposed a novel model based on Graph Convolutional Networks to predict the total runtime of a given application on different machine configurations. The model achieves a prediction accuracy of 87%. Third, they developed a new formulation for optimizing cloud deployments in order to reduce deployment costs while meeting deadline constraints. Their pseudo-polynomial optimal solution using a multi-choice knapsack mapping reduces costs by 35.29%.

Northeastern University (USA) proposed a novel weight pruning framework for ReRAM-based mixed-signal DNN accelerators, named TinyADC, which effectively reduces the required bits for ADC resolution and hence the overall area and power consumption of the accelerator without introducing any computational inaccuracy. Compared to state-of-the-art pruning work on the ImageNet dataset, TinyADC achieves 3.5X and 2.9X power and area reduction, respectively. TinyADC framework optimizes the throughput of state-of-the-art architecture design by 29% and 40% in terms of the throughput per unit of millimeter square and per unit of watt, respectively.

Xilinx Research (Ireland) described a co-design method to construct a neural network and an FPGA-based inference engine at the same time, for extreme high-throughput data rates. Called LogicNets, the method creates a set of layer primitives called neuron equivalent circuits (NEQs) which map neural network layers directly to the hardware building blocks (HBBs) available on an FPGA. From this, it is possible to design an execute networks with low activation bitwidth and high sparsity at extremely high data rates and low latency, while only using a small amount of FPGA resources.

The paper presented by Princeton University (USA) generalizes Instruction-Level Abstractions (ILAs) for specification of general hardware modules and formal verification of their RTL implementations. This includes automated generation of a complete set of functional (not including timing) specification properties using the ILA instructions. The work includes a case study on an open-source 8051 micro-controller, where verification identified three bugs and completed in reasonable time.

The German Research Center for Artificial Intelligence presented a paper in which Metamorphic Testing is expanded to verify Analog/Mixed-Signal (AMS) systems. As a challenging AMS system, an industrial phase-locked loop was considered. The team found a critical bug in the industrial PLL which clearly demonstrates the quality and potential of MT for AMS verification.

University of Liverpool (UK) proposed a differential aging sensor to detect recycled ICs. The solution employs ring oscillators with sub-threshold leakage current to detect aging effects using bias temperature instability (BTI) and hot carrier injection (HCI) on a 22-nm CMOS technology, provided by GlobalFoundries. Simulation results confirm the ability to detect recycled ICs with high confidence. It is shown that the discharge time increases by 14.72% only after 15 days and by 60.49% after three years’ usage.

University of Applied Sciences Technikum Wien (Austria) addressed the systematic fault injection into the configuration memory of SRAM-based FPGAs as a way to gain insight into the criticality of individual configuration bits. Current approaches implicitly assume that results obtained on one FPGA device can be generalized to all devices of that type. This work challenges that assumption. To that end, a synthetic test design was subjected to systematic fault injection on sixteen Xilinx Artix-7 as well as ten Lattice iCE40 FPGAs. The results indicate that the derived sets of critical configuration bits vary from device to device of the same type, especially if the interconnect is targeted.

Indian Institute of Technology Ropar addressed the malicious application which can potentially threaten data privacy in multicore systems leveraging the dynamic partitioning schemes applied to the Last Level Caches, by creating a timing-based covert channel attack. The malicious applications may contain a trojan and a spy and use the underlying shared memory to create the attack.

One of the themes addressed by the conference was security issues related to FPGA multitenancy in cloud acceleration. FPGAs are now part of the cloud acceleration-as-a-service portfolio offered by major cloud providers. Cloud is naturally a multi-tenant platform. Recent research works showed how a malicious cloud user can deploy remotely-controlled attacks to extract secret information from the FPGA co-tenants or inject faults.

The DATE Conference 2021 proceedings are already available for registered attendees, and will be publicly available in two years from now.

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