New testing challenges take center stage at the International Test Conference 2020

Smaller process geometries, multibillion-transistor designs, zero-defect requirements, emerging memories, new security threats: technology advancements and evolving application constraints make chip testing increasingly challenging and increasingly important. Researchers around the world, in the semiconductor industry and in the academia, struggle to overcome these new challenges – aiming to ensure effective chip testing while preserving the best possible PPA results and optimizing the use of testing resources. Every year, the International Test Conference offers a wide selection of some of the best research works in this area, and the 2020 edition – which took place as a virtual event from November 3^rd to 5^th, sponsored by IEEE and the IEEE Philadelphia Section – was no exception. This week, EDACafe quickly browses through the proceedings of ITC 2020, peeking into a few sample papers just to give a sense of the new challenges confronting test engineers, and a taste of the new solutions that are being proposed.

AI-based test techniques

A transversal theme at ITC 2020 was the use of techniques based on artificial intelligence to improve different aspects of the testing process. Several papers focused on using AI to improve fault diagnosis when limited fault data is available. For example, two papers from Carnegie Mellon University addressed yield improvement applications, one of them presenting a solution based on ‘transfer learning’ from prior knowledge, with the goal of reducing the cost of collecting data from failing ICs, and the other a machine learning-based method for improving IC diagnosis using tester and simulation data. A method based on a Gaussian Naïve Bayes trained model was proposed by a team from University of Montpellier, École Centrale de Lyon and STMicroelectronics, to improve the prediction of good defect candidates in the diagnosis of observed failures in automotive SoCs, reducing the use of Physical Failure Analysis (PFA). Researchers from UCSB and NXP devised a method for advanced outlier detection using unsupervised learning for screening potential customer returns, addressing the problem of the extreme scarcity of customer failure data.

Neural networks can also be deployed to enhance automatic test pattern generation (ATPG) by reducing backtracks: a work on this subject was presented by a team from Auburn University.

Besides test proper, AI-based techniques can be used to prevent chip malfunction. A team from Osaka University proposed a proactive method for mitigating supply noise that can cause failures in power-hungry processors. The method employs a short-term current predictor based on machine learning, trained on the current draw profiles for different CPU instructions. But even hackers could potentially take advantage of artificial intelligence: a team from University of Maryland Baltimore County, Institut Polytechnique de Paris and French company Secure-IC showed the possibility of cross-PUF attacks in which a particular PUF’s power fingerprints can be used to break another PUF’s security, using the power side-channel to train a machine learning model.

On-chip test structures, new test generation techniques

Advancements are obviously taking place in ‘conventional’ (non AI-based) testing techniques, too. For example, a team from Mentor and Intel discussed the benefits of Streaming Scan Network (SSN), a bus-based scan data distribution architecture designed to address the challenges posed by SoC designs that are increasingly difficult to test using traditional scan access methods – as the number of cores keeps growing while chip pin counts available for scan remain constant or decline. And researchers from Georgia Institute of Technology, Auburn University, and Intel addressed the problem of novel defect mechanisms – partial opens and partial shorts – in advanced process nodes, which make the test generation process very challenging.

Testing for yield improvement

Advanced process nodes and the increasing memory content of SoCs are posing new challenges in fault diagnosis and correction when it comes to improve the yield of the chip manufacturing process. Carnegie Mellon University proposed a new version of its Logic Characterization Vehicle (CM-LCV) to compensate for the lower diagnosis capability caused by high defect densities that are now very common during production ramping. As for memories, redundancy-based repair is today even more important, but redundancy analysis (selecting the best repair solution) is a difficult process because of the lack of specific benchmarks. Korean researchers from Yonsei University and SK Hynix therefore proposed a fail memory configuration set for redundancy analysis estimation. Another shortcoming of existing redundancy-based memory repair methods is their impact on chip area (addition of ad hoc logic) and test time. Researchers from Mentor came up with a strategy based on merging failure information coming from different memories or segments of memories tested to calculate a common repair solution which can be broadcasted.

Testing for reliability improvement

High reliability automotive applications require new test techniques to minimize device failures in the field. For example, a team from Intel and Synopsys addressed the problem of DRAM failures, proposing a mitigation solution based on ECC (Error Correcting Codes). Several papers concerned the requirements of the ISO 26262 standard; among them, STMicroelectronics and Synopsys discussed the implication of this standard on conventional test and diagnosis flows. NXP, for its part, proposed a wafer level stress solution for enabling zero defect quality for automotive microcontrollers without package burn-in. A team from Kyushu Institute of Technology, Paderborn University and University of Stuttgart developed a logic fault diagnosis technique that is able to identify hidden delay defects by analyzing fail logs produced by Faster-than-At-Speed Testing. The target here is to achieve a quick ‘reliability ramp-up’ of a manufacturing process, distinguishing defective chips from chips that are slow due to parameter variations. Failures affecting GPUs – devices increasingly used in automotive applications, too – were the subject of papers from Hitachi and Osaka University, and from Nvidia.

Testing for security issues

New test challenges are also being posed by security threats inherent to the fabless chipmaking process, that involves sourcing IP blocks and foundry services from a variety of subjects in different countries. For example, researchers from University of Florida addressed the issue of hardware Trojan detection. Trojans can be inserted into design files by modifying existing functionality, or by adding circuitry into unused areas. The team has developed a laser probing approach to nondestructively detect Trojans only using the clock activity as its input. And researchers from Duke University and IBM Thomas J. Watson Research Center presented a logic-locking technique that utilizes built-in self-test (BIST) to isolate functional inputs when the circuit is locked, with the benefits of a small silicon area overhead and no delay or power impact.

Testing emerging devices

Several papers addressed the testing challenges posed by emerging devices, such as AI accelerators (Duke University, Intel), 2.5D high bandwidth memory subsystems (Rambus), STT-MRAMs (TUDelft, CognitiveIC, Imec), eMRAMs (Mentor, Arm), ReRAM-based computing systems (Duke University), memristor-based crossbar for neuromorphic applications (Indian Institute of Technology, Nanyang Technological University Singapore), etc.

This concludes our quick look at some sample papers from the 2020 International Test Conference. The event obviously offered many more papers, a wider range of topics, and a rich program including tutorials, workshops etc. ITC content is available on-demand through November for registered attendees.

This entry was posted on Tuesday, November 10th, 2020 at 12:06 am. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.