Despite the virtual format, the 2020 Fall edition of the Linley Processor Conference – organized by the technology analysis firm Linley Group – is offering its biggest program ever, with 33 technical talks across six days: October 20 to 22, and October 27 to 29. The high number of presentations confirms that these are really exciting times for innovative processing architectures. In his keynote, Linley Gwennap – Principal Analyst of The Linley Group – explained the proliferation of application-specific accelerators describing them as a way to extend Moore’s Law, since moving to the most advanced process nodes now offers little benefit. In this article, EDACafe is providing a quick overview of some of the presentations which were given during the first part of the event, mainly focusing on new announcements; next week we will complete our coverage with an overview of the second part of the conference.
Flex Logix’s InferX X1 chip, announced at the 2019 Linley Fall Conference, is now available. According to the company, the device is 3-18 times more efficient than Nvidia’s GPU architecture for large models with megapixel images, and is also much more efficient in terms of throughput per square millimeter of die area: it measures 54mm2 compared to 545mm2 for Nvidia Tesla T4. Flex Logix claims that the InferX X1 runs faster than Nvdia’s Xavier NX on real customer models at much more attractive prices: from $99 to $199 (1KU quantity), depending on speed grade.
Credit: Flex Logix
Brainchip, which offers a neuromorphic System-on-Chip introduced at last spring edition of the Linley Conference, has added details on “activation sparsity” and “activity regularization”. Activation sparsity is the percentage of zero-valued entries in the previous layer’s activation maps; higher activation sparsity yields fewer operations. CNNs converted to event-domain (i.e. spiking networks) automatically start at 40-60% activation sparsity due to the use of ReLU and batch normalization; Brainchip further increases activation sparsity by using activity regularization during training. Activity regularization is the process of adding more information to the loss function to balance the model’s accuracy and activation sparsity. Increasing activation sparsity, activity regularization further reduces computation.
Catching up on some of the news from the last thirty days or so, this week’s focus is on both EDA-related innovations and on new process materials/equipment. Completing our updates, some application-specific news and several acquisition announcements.
SoC Lifecycle Management
Product lifecycle management (PLM) – a long established concept in the avionics and automotive industries – is becoming increasingly important for the development of SoCs. Two recent announcements highlight different aspects of PLM solutions targeted at SoCs: IP management and post-silicon analysis, respectively. Methodics IPLM 3.0 is the new version of the IP lifecycle management platform developed by Methodics, a company that was acquired by Perforce earlier this year. Aimed at managing the planning process of SoCs, the new platform allows what-if analysis of early design prototypes (build vs. buy vs. reuse of IP), and automates the delivery of an IP bill of materials (BoM) to development teams.
Methodics IPLM also adds new security solutions addressing the concerns related to sharing IP and global IP leakage. Synopsys, for its part, has recently unveiled its Silicon Lifecycle Management (SLM) platform, described as “the industry’s first data-analytics-driven approach to optimizing SoCs from the design phase through to end-user deployment.” The Synopsys SLM platform is based on two principles: 1) gather as much useful data about each chip as possible, by adding information obtained through monitors and sensors that are embedded in the chip; 2) analyze that data throughout the chip’s entire lifecycle using analytics engines to enable optimizations at each stage of the semiconductor lifecycle, up to in-field operation.
With Arm priced at $40 billion, the pun was inevitable: “Somebody just said to me the other day: you paid an arm and a leg!” Nvidia’s CEO Jensen Huang recalled this joke during a ‘fireside chat’ with Arm’s CEO Simon Segars, on occasion of the Arm DevSummit – a developers’ conference that took place as a virtual event from October 6th to 8th. Despite the joke, Huang is happy with the deal: “[It’s] worth every penny and more,” he soon added. While we wait for updates on another big deal – AMD reportedly in advanced talk to buy Xilinx – the answers provided by Huang and Segars offer the official CEOs’ perspective on the Nvidia acquisition of Arm.
The “fireside chat” which took place during the Arm DevSummit [virtual event]. From left to right: moderator Rene Haas, Arm CEO Simon Segars, Nvidia CEO Jensen Huang. Image credit: Arm
Expanding the reach of Nvidia AI software to the whole footprint of Arm-based silicon
This deal is clearly different from most semiconductor acquisitions, usually involving two chip vendors. On the one hand, Arm is a pure-play IP licensor; on the other hand, while the business of Nvidia includes designing processor and selling chips, its technological involvement in the deal mainly concerns its AI software capabilities. “We’re going to be able to bring our capability to the Arm ecosystem, and Arm will be able to give our accelerated computing a reach like never before,” Huang said. “Nvidia has deep artificial intelligence capability, we know how to write the software of artificial intelligence,” he added. “No computing platform has the reach of Arm […], and so the combination [of the two companies] I think is just incredibly powerful that way.” Segars confirmed that Nvidia is going to bring mostly its AI software to the table: “Computers are useless without the software that runs on them,” he said, “ and we are [moving to] a world of AI where software is writing software, software is checking software, software is learning from data […]. I think between us putting the strengths of the companies together, we’re going to be able to address that.”
As reported by EDACafe last July, Mentor has extended their Recon technology to the Calibre nmLVS circuit verification platform. The resulting product is called Calibre nmLVS-Recon, where LVS stands for Layout Versus Schematic, and Recon stands for reconnaissance. This week we will take a closer look at this new tool with the help of Hend Wagieh, a Senior Calibre Product Manager at Mentor, a Siemens business. In the video interview that Wagieh has recently given to Sanjay Gangal from EDACafe, a number of topics concerning Calibre nmLVS-Recon have been addressed. Wagieh set up the context by briefly recapping what Calibre is about: a comprehensive platform for design automation and design analysis, which includes a number of tools for physical verification, circuit verification, parasitic extraction, yield enhancing. According to Wagieh, Calibre is used by “twenty-three out of the top twenty-five” companies designing chips worldwide.