Smaller process geometries, multibillion-transistor designs, zero-defect requirements, emerging memories, new security threats: technology advancements and evolving application constraints make chip testing increasingly challenging and increasingly important. Researchers around the world, in the semiconductor industry and in the academia, struggle to overcome these new challenges – aiming to ensure effective chip testing while preserving the best possible PPA results and optimizing the use of testing resources. Every year, the International Test Conference offers a wide selection of some of the best research works in this area, and the 2020 edition – which took place as a virtual event from November 3rd to 5th, sponsored by IEEE and the IEEE Philadelphia Section – was no exception. This week, EDACafe quickly browses through the proceedings of ITC 2020, peeking into a few sample papers just to give a sense of the new challenges confronting test engineers, and a taste of the new solutions that are being proposed.
