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Archive for October 19th, 2020

PLM; Ru interconnect; CNT pellicles; Intel-Sandia collaboration; 10Mbps Ethernet on a twisted pair

Monday, October 19th, 2020

Catching up on some of the news from the last thirty days or so, this week’s focus is on both EDA-related innovations and on new process materials/equipment. Completing our updates, some application-specific news and several acquisition announcements.

SoC Lifecycle Management

Product lifecycle management (PLM) – a long established concept in the avionics and automotive industries – is becoming increasingly important for the development of SoCs. Two recent announcements highlight different aspects of PLM solutions targeted at SoCs: IP management and post-silicon analysis, respectively. Methodics IPLM 3.0 is the new version of the IP lifecycle management platform developed by Methodics, a company that was acquired by Perforce earlier this year. Aimed at managing the planning process of SoCs, the new platform allows what-if analysis of early design prototypes (build vs. buy vs. reuse of IP), and automates the delivery of an IP bill of materials (BoM) to development teams.

Methodics IPLM also adds new security solutions addressing the concerns related to sharing IP and global IP leakage. Synopsys, for its part, has recently unveiled its Silicon Lifecycle Management (SLM) platform, described as “the industry’s first data-analytics-driven approach to optimizing SoCs from the design phase through to end-user deployment.” The Synopsys SLM platform is based on two principles: 1) gather as much useful data about each chip as possible, by adding information obtained through monitors and sensors that are embedded in the chip; 2) analyze that data throughout the chip’s entire lifecycle using analytics engines to enable optimizations at each stage of the semiconductor lifecycle, up to in-field operation.

Synopsys Silicon Lifecycle Management Platform. Credit: Synopsys

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