A closer look at Mentor’s Calibre nmLVS-Recon

As reported by EDACafe last July, Mentor has extended their Recon technology to the Calibre nmLVS circuit verification platform. The resulting product is called Calibre nmLVS-Recon, where LVS stands for Layout Versus Schematic, and Recon stands for reconnaissance. This week we will take a closer look at this new tool with the help of Hend Wagieh, a Senior Calibre Product Manager at Mentor, a Siemens business. In the video interview that Wagieh has recently given to Sanjay Gangal from EDACafe, a number of topics concerning Calibre nmLVS-Recon have been addressed. Wagieh set up the context by briefly recapping what Calibre is about: a comprehensive platform for design automation and design analysis, which includes a number of tools for physical verification, circuit verification, parasitic extraction, yield enhancing. According to Wagieh, Calibre is used by “twenty-three out of the top twenty-five” companies designing chips worldwide.

Early integration – and new problems

Layout Versus Schematic is the step where designers and verification teams compare the physical implementation of their design to the schematic, to make sure that the electrical characteristics of the final chip will correspond to their initial intent. As Wagieh pointed out in the video interview, Calibre nmLVS-Recon specifically targets the challenges posed by this type of circuit verification at the early design stage. The need to start verification earlier reflects a ‘shift left’ approach in the chip integration stage of the design flow. Traditionally – Wagieh explained – designers used a bottom-up flow: they started off by working on individual blocks or specific IC partitions, and integration of all these elements only took place when blocks were completed.

Today this is not the case anymore, because of the increased pressure towards the reduction of time-to-market. Several activities are now happening in parallel: as Wagieh pointed out, “designers are not waiting until the blocks are complete in order to start their integration.” But this shift-left approach involves several new potential problems. Examples cited include incomplete top-level routings, specific partitions of the blocks still missing, etc. “Yet the SoC or the IC is still going through full iteration – running circuit verification, DRC etc.,” she added. As a consequence, designers are faced with millions of systematic errors that they are not ready to fix yet. This is where Calibre nmLVS-Recon can help.

Focusing on early design needs only – specifically on shorted nets

The new Mentor product specifically aims at helping designers address these challenges. As Wagieh explained, it allows designers and verification teams to focus only on what they need in early design stage. It performs “a very focused analysis, discarding all the unneeded data” and the aspects that designers are not ready to look at yet. This quick exploration of the design enables a faster and focused iteration-based use model, significantly accelerating the circuit verification iterations. According to Wagieh, this provides engineers a “fast feedback that enables them to quickly analyze, fix and verify selected design issues.” And there is one specific problem where the new product promises to be a great help: shorted nets. According to Mentor, design teams spend the majority of their LVS debug time on addressing the shorted nets. Each shorted path needs to be analyzed and fixed to avoid the risk of a short circuit in the design.

Samsung’s endorsement

Samsung has publicly endorsed Calibre nmLVS-Recon, with a quote included in the Mentor press release announcing the new product. As the EDACafe video interview revealed, this endorsement reflects a collaboration that was important in the development of the new product. Samsung was one of the earliest foundries to engage with Mentor, whose R&D has been working on the LVS-Recon flow for quite some time. According to Wagieh, Samsung is unique among foundries in that they get access to many of their internal designs from their own design team – as opposed to other foundries, that usually get access to their customers’ designs only when they are ready for manufacturing. Completed designs are not the target of Calibre nmLVS-Recon, which focuses on “very dirty, immature, early designs.” Mentor worked with Samsung to test the flow and get feedback using the Korean company’s internal designs, and Samsung saw “extreme benefits”: as revealed by the video interview, the foundry was able to cut the run time around 10x. Samsung also wanted to make the LVS-Recon flow available to both company’s mutual customers, and to be the first foundry to enable the flow as part of their certified PDKs.

Track record and innovations

According to Wagieh, Calibre LVS – which the nmLVS-Recon is today an extension to – has been the de facto standard in its market for over fifteen years, being used by all the key semiconductor companies worldwide and all the foundries as well. Benefits she cited include reliability, “very competitive runtime, best-in-class accuracy, lean hardware and computation resources.” Wagieh also pointed out that Mentor releases a new Calibre version every quarter. One of the major innovations introduced before Calibre nmLVS-Recon was Calibre DRC-Recon, a tool focusing on the early physical verification design issues. More new tools are expected in future releases.

The development process

Calibre nmLVS-Recon is already available. As Wagieh recalled, Mentor has been working on it for “quite a while”. Collaboration with beta customers allowed Mentor to test it early in the flow and get feedback, in order to crystallize all the product features. “So now we’re ready,” she pointed out. “It’s available for customers to play with, and start experiencing the benefits that other customers have been seeing over the last few months. Calibre nmLVS-Recon makes everybody’s life easier; designers and engineers can achieve more and more inclusive circuit verification cycle faster. And it helps companies realizing a faster time to market for their products,” Wagieh concluded.

The knowledge base provided by Mentor for the designers that are interested in knowing more about Calibre nmLVS-Recon. includes a datasheet, a video, and an on-demand webinar.

Categories: EDACafe Editorial, Video Interview

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