Semiconductor industry now “barely in the 18 nm generation” according to IEEE

Using the correct definition of technology node, today’s 5-nanometer generation actually corresponds to the 18-nanometer node. This is one of the key messages conveyed by the 2020 edition of the IEEE International Roadmap for Devices and Systems (IRDS). Building on what until 2015 was called ITRS (International Technology Roadmap for Semiconductors), the IRDS is an authoritative IEEE initiative with a proven track record of reliably predicting future technology challenges and solutions: for example, the transformation of the planar silicon gate CMOS to strained silicon, high-κ/metal-gate and FinFET was predicted by the ITRS as early as in 1998. In hundreds of content-packed pages, the recently released 2020 IRDS edition obviously covers many more topics, but the energy devoted by the authors to the node nomenclature issue – and the amount of exclamation points they used – deserve some extra attention.

From metal half pitch to a marketing label

Recapping the evolution of the node definitions, the IRDS authors remind readers that from 1992 to present the IC feature considered by ITRS and IRDS to name technology nodes was half pitch of the tightest metal layer, which in the past essentially coincided with the gate length. However, in the 90’s, due to the marketing pressure for a more aggressive nomenclature, the industry started using a node definition based on the average of half-pitch and gate length. Later on, some companies decided to use only the gate dimension to define the name of the technology node; and finally – according to the IRDS authors – “the technology node definition became 70% of whatever the name of the node of the previous generation was!” Therefore, the current nomenclature “has led to a complete detachment between IC features and technology nodes’ names.” As a result, the IRDS authors insist, today’s industry labeling of nodes “clearly appears completely devoted of any connection to reality.”

Are today’s most advanced devices 5-nanometer or 18-nanometer?

In the words of IRDS authors, the most advanced logic products shipped in 2020 have “a minimum metal pitch of 36 nm (corresponding to the 18 nm technology node definition according to NTRS/ITRS and IRDS nomenclature)” (…) “This means that this year (2020) the semiconductor industry is in the 18 nm generation using the correct definition of technology node.” They continue, “Silicon manufactures still insist in calling this technology ‘the 5 nm node’ even though these node numbers do not correspond to any meaningful and measurable quantity related to transistor density on the wafer!”

Realistic node nomenclature explains why Moore’s law is still alive

Industry labeling of nodes also makes the end of Moore’s law appear closer than it really is. As noted by the IRDS authors, “there are companies nowadays announcing the introduction in the non-too-distant future of technologies below 1 nm in this decade!?” If the 1-nanometer threshold were actually that close, maybe the industry would already be implementing some radically new alternatives to scaling, which is not happening yet. And this is no surprise, according to the IRDS authors: “No wonder Moore’s Law will be still valid for the next 10 years once the real numbers of IC features are used for node definition; there is still a lot of room to run for scaling as a contributor to increasing transistor density!”

Feature scaling to reach its limits at the end of this decade

Having said that, the IRDS obviously concedes that scaling will eventually run out of gas. As the authors point out, “Both the 2020 IRDS and ASML predict that the ability to reduce features (line and space) would reach final limits around 7-8 nm by the end of this decade.” This sentence clearly implies that – according to IRDS – the ‘real’ 7-nanometer node will only be achieved around 2030. But when lithography limits will be reached, “resolution may not be any longer a major limiter by then due to the likely introduction of several types of 3D device structures into manufacturing.” According to IRDS, “The new potential patterning challenges will thus be related to cost, yield, defectivity, and optimization of complex 3D structures. Etch and deposition of sub 10 nm structures will also become major challenges. Another potential challenge might be implementing patterning on 450 mm wafers. However, as EUV becomes mainstream patterning method providing substantial cost reduction it could limit the financial benefit of switching to 450 mm wafers.”

From here to 2030: towards IC vertical integration

The roadmap provides a consistent perspective on the many innovations in transistor and chip architectures that are expected during this decade. According to the IRDS authors, “Beyond 2022 a transition from FinFET to gate-all-around (GAA) will start and potentially a transition to vertical nanowires devices will be needed when there will be no room left for the gate length scale down due to the limits of fin width scaling (…) and contact width.” The industry is moving towards “the ideal 3D MOS transistor”, but 3D implementation will happen in steps. “The MOSFET device architecture has been changing from the planar 2D through 2.5D of FinFET to GAA either of nanowire or nanosheet structures. These GAA MOSFETs will be stacked monolithically to be 3D VLSIs.”

System integrators leadership, thermal-limited clock frequency

Thanks to its historical perspective, the IRDS also helps recapping the evolution of the different electronics and IT market segments, enabling readers to get the big picture. For example, authors recall that “with the advent of the fabless/foundry ecosystem the system integrators regained the leadership position in establishing device requirements”. Therefore, “No longer does a faster microprocessor trigger the design of a new PC but on the contrary the design of a new smart phone generates the requirements for new ICs and other related components.” An historical perspective is also provided to explain why processor clock frequency is still in the range of a few gigahertz, “even though transistor performance could have easily allowed circuits to operate in the tens of GHz and above”. As the authors recall, at the beginning of the past decade it became clear that “one of the two features (i.e., either the frequency or the number of transistors) had to level off in order to make the ICs capable to operating under practical thermal conditions. Frequency was selected as the sacrificial victim.” In turn, “These power limitations compelled a dramatic change in processor architecture to multicore.”

Free download

Presented last 2-3 September at the IEEE International Nanodevices & Computing Conference (a virtual event), the 2020 edition of the International Roadmap for Devices and Systems includes thirteen major documents totaling over 700 pages, covering many more topics such as quantum computing, factory integration, metrology, outside system connectivity, advanced packaging etc. All documents can be downloaded for free after free registration.

Credit: IEEE

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