Geopolitical tensions keep on influencing the semiconductor industry. Huawei is reportedly trying to convince Samsung and TSMC to build an advanced chip fab without using U.S. equipment; and former Risc-V Foundation – now called “Risc-V International” – has recently incorporated in Switzerland, a move preannounced by Chief Executive Calista Redmond in this interview. But now, back to technology.
Deploying autonomous vehicles at scale will require systems redundancies
A recent blog post from Amnon Shashua, CEO of Mobileye, provides several important concepts about the future of autonomous vehicles and his company’s strategy. The key point stressed by Shashua is that “safety must dictate the software and hardware architecture in ways that are not obvious.” Mobileye has already addressed the safety issues linked to the AV decision-making process: the possibility of uncareful driving has been ruled out by clarifying, in a formal manner, what it means to be “careful” (e.g. when merging into traffic); and the need to make predictions about behaviors of other road users has also been ruled out, by always assuming the worst-case scenario. This approach is also being used as a basis for the new IEEE 2846 standard. Having fixed the decision-making process, the only other possible cause of accidents is a glitch in the perception system, whose minimum MTBF requirement depends on the maximum acceptable accident frequency. This is where scale comes into play, as the absolute number of accidents involving autonomous vehicles obviously depends on how many of them are circulating on the roads. In the example provided by Shashua, a fleet of 100,000 robotic shuttles, achieving a maximum frequency of one accident every quarter would require a perception system with an MTBF of 50 million hours of driving – one thousand times better than the error rate of a human driver. In Mobileye’s view, such an ambitious MTBF can only be obtained by introducing system redundancies, as opposed to sensor redundancies within the system. This means equipping the vehicle with two independent and different perception systems: one based on cameras only, and the other on radars/lidars only. The probability of both systems failing at the same time is extremely low. This is why Mobileye is not pursuing the sensor fusion approach; instead, the company has developed a camera-only perception system. Which, by the way, works very well, as shown by this new 40-minute unedited video shot in Jerusalem.
Amnon Shashua. Image credit: Intel
New Arm processor IP
On May 26 Arm announced four new IP mostly targeting 5G mobile applications, offering significant advances over corresponding previous Arm processors. Cortex-A78 is a CPU for smartphones and other mobile devices, offering a 20% increase in sustained performance over Cortex-A77-based devices within a 1-watt power budget. Cortex-X1 – the most powerful Cortex CPU to date, with a 30% peak performance increase over Cortex-A77 – is the first CPU from the new Cortex-X Custom Program, which allows for customization and differentiation beyond the traditional roadmap of Arm Cortex products. Mali-G78 GPU will deliver a 25% increase in graphics performance relative to Mali-G77, with support for up to 24 cores. Ethos-N78 neural processing unit (NPU) delivers greater on-device ML capabilities and up to 25% more performance efficiency compared to previous Ethos-N77 NPU.
Image credit: Arm
Both Synopsys and Cadence are already providing support for the above-mentioned new Arm IP. Synopsys has enabled tapeouts of optimized system-on-chips for early adopters of Cortex-A78, Cortex-X1 and Mali-G78. Synopsys support includes QuickStart Implementation Kits (QIKs) available today. Cadence is supporting Cortex-A78 and Cortex-X1 with a digital full flow Rapid Adoption Kit (RAK); in addition, the Cadence Verification Suite and its engines have been optimized for the creation of designs based on these two new CPUs.
DARPA appoints research teams to develop security-aware EDA tools
Moving from PPA to PPAS – where S stands for security – when exploring trade-offs or setting design constrains for a new SoC. The goal of DARPA’s AISS program (Automatic Implementation of Secure Silicon) could be described this way, even though the DoD agency uses a different acronym (PASS, meaning Power, Area, Speed, and Security). The AISS program aims at providing SoC designers with new EDA tools that will allow them to specify security constraints, which will then be automatically satisfied by generating the optimal implementation. These future “security-aware EDA tools” will combine an advanced security engine developed within the AISS program, with commercial off-the-shelf IP from Synopsys, Arm, and UltraSoc. DARPA has recently announced the two research teams selected to develop this initiative: one includes Synopsys, Arm, Boeing, Florida Institute for Cybersecurity Research at the University of Florida, Texas A&M University, UltraSoC, and University of California, San Diego; while the members of the other team are Northrop Grumman, IBM, University of Arkansas, and University of Florida. AISS addresses four fundamental silicon security vulnerabilities: side channel attacks, hardware Trojans, reverse engineering, and supply chain attacks (such as counterfeiting, recycling, re-marking, cloning, and over-production).
The DARPA AISS program. Image credit: DARPA
Backscattering startup gets seed financing
Transmitting IoT data by “hitchhiking” existing RF signals generated by wireless devices already present in the environment: backscattering could be described this way. This technology is moving from academic research – with works such as the one from the University of California San Diego, presented at the ISSCC 2020 conference – to real products. HaiLa Technologies, a Canadian semiconductor startup that has recently raised $5 million in seed financing, plans to provide early access to the first Wi-Fi IP core based on its backscatter technology by the end of 2020. This will enable companies to develop the next generation of ultra-low power chipsets for IP over Ethernet over Wi-Fi in the IoT space. HaiLa uses a proprietary backscattering technique which allows modulation of digital sensor data on top of ambient signals of different protocols while maintaining the integrity of the signal to the original specific protocol. According to the company, this ensures compatibility of Haila sensor tags to various existing wireless protocols, resulting in a drastic reduction in deployment costs and risks. One of the technical advisors of Haila is Dinesh Bharadia, a professor at the UC San Diego who co-led the above-mentioned research work.
News related to artificial intelligence abound this week – including a notable research work that promises to reduce training energy consumption up to one-tenth. Before proceeding to this week’s news roundup, let’s briefly mention that – as widely reported by the media – on May 15thTSMCannounced its intention to build and operate a 5-nanometer fab in Arizona. The news has spurred a lot of comments, such as the ones reported in this EETimes article.
EDA updates: Cadence, Mentor, Synopsys
Cadence has made available ten new Verification IP (VIP) solutions supporting the development of SoCs and microcontrollers for automotive, hyperscale data center and mobile applications, including CXL, HBM3, TileLink and MIPI CSI‑2sm 3.0. Also available from Cadence, a 56G long-reach SerDes IP on TSMC’s N7 and N6 process technologies. And on its part, TSMC has granted certifications for its N5 and N6 process technologies to Mentor – for a broad array of IC design tools – and to Synopsys – for digital and custom design platforms.
Investments and technology innovation are the common underlying themes of this week’s news roundup – with the recent announcement from Intel Capital, some details about the BNN approach pursued by a Japanese startup, and an overview of San Francisco Bay Area venture capital deals in first quarter 2020. Innovations – namely, social distancing wearables – are also being developed to combat the Covid-19 pandemic.
New addition to Intel Capital’s portfolio
Astera Labs, Axonne, and Xsight Labs are the three silicon startups included in the group of eleven companies now joining Intel Capital’s portfolio. Astera Labs (Santa Clara, CA) is described by Intel as “a fabless semiconductor company that develops purpose-built connectivity solutions for data-centric systems to remove performance bottlenecks in compute-intensive workloads such as artificial intelligence and machine learning.” As explained in Astera’s website, the company’s key products are “smart retimers” based on an “innovative low-latency architecture”; these devices are “designed to easily eliminate signal integrity issues for PCI-Express (PCIe) 4.0 and 5.0 interconnects in data-centric applications.” Axonne (Sunnyvale, CA) develops high-speed Ethernet network connectivity solutions for automobiles. The company website provides no further details; according to Intel, however, Axonne solutions make use of “proprietary mixed signal circuits, algorithms and digital signal processing”. Just as secretive is the website of Israel-based Xsight Labs; the Intel press release states that the company “provides new chipset designs” aimed at “accelerating next generation, cloud-based, data-intensive workloads”. The group of eleven companies joining Intel Capital’s portfolio, all described by Intel as “startups”, also includes ProPlus Electronics, a Chinese EDA company that – according to the company’s website – was founded in 2006. Tools cited in the ProPlus website include SPICE modeling, giga-scale SPICE simulations, and a “Design-for-Yield” solution.
Image credit: Intel Capital
Retaining accuracy in binary neural networks: the LeapMind approach
As recently reported by EDACafe, one of the current trends in artificial intelligence is the growing adoption of Binary Neural Networks (BNNs), where weights can only be zero or one. This approach reduces power and storage space relative to INT8 weights, still achieving a good accuracy. New BNN intellectual property is now offered by Tokio-based LeapMind with its “Efficiera” design, an ultra-low power AI inference accelerator IP targeting ASIC and FPGA circuits at the edge. Using 1 bit for weights and 2 bits for activation, the Efficiera IP implemented in a 12 nanometer TSMC process achieves a power efficiency of 27.7 TOP per Watt, a performance of 6.55 TOP per second at 800MHz, and an area of 0.442 square millimeters. LeapMind places special emphasis on new techniques aimed at retaining accuracy in binary neural networks. Some of these techniques – such as quantization-aware training and “pixel embedding” to quantize the first convolution layer – are described in this article, which includes the slides (in English) used by Hiroyuki Tokunaga, CTO of LeapMind, is his keynote speech for the recent CoolChips 23 virtual event.
Image credit: LeapMind
Beyond silicon: first quarter VC deals in the San Francisco Bay Area
As an update to our February 7th article, let’s take a quick look at Q1 2020 venture capital deals concerning tech companies based in the San Francisco Bay Area. Once again, we extracted the relevant data from the MoneyTree report published by PricewaterhouseCoopers and CB Insights – this time from the Q1 2020 edition; and once again, most of the companies cited below do not belong to the semiconductor industry. In the first quarter of this year, all five largest US investment rounds from venture capital – each above $450 million – involved Bay Area companies: JUUL Labs (electronic cigarettes, San Francisco), Joby Aviation (electric vertical takeoff and landing aircrafts, Santa Cruz), Impossible Foods (“meat from plants”, Redwood City), Lyell Immunopharma (cell-based immunotherapies, South San Francisco), and Snowflake Computing (cloud data platform, San Mateo). Accounting and finance startups saw largest M&A “exits” in first quarter 2020, and four out of five top US deals involve companies based in the Bay Area: Credit Karma (free access to personal credit scores, San Francisco), acquired by Intuit; Plaid Technologies (fintech APIs, San Francisco), acquired by Visa; Vlocity (industry-specific cloud and mobile software, San Francisco), acquired by Salesforce; and Armis (agentless device security, Palo Alto), acquired by Insight Partners. Two Bay Area companies are among the first quarter’s top five IPOs: One Medical Group (membership-based primary care practice, San Francisco) and Revolution Medicines (novel cancer drugs, Redwood City). As for emerging areas (artificial Intelligence, cybersecurity, supply chain tech, robotics, smart cities, InsurTech), top US deals in the first quarter include Pony.ai (autonomous driving technology, Fremont), Netskope (cloud security, Santa Clara), SambaNova Systems (AI system platform, Palo Alto), SentinelOne (enterprise cybersecurity, Mountain View), Sysdig (security for cloud-native DevOps workflows, San Francisco), Arctic Wolf Networks (cybersecurity services, Sunnyvale), Molekule (air purifiers, San Francisco), Cepton Technologies (lidar-based solutions, San Jose). Let’s close with the most active US venture capital firms in first quarter 2020. Four out of seven top VC firms are headquartered in Sand Hill Road (Menlo Park): Khosla Ventures, Andreessen Horowitz, New Enterprise Associates, Kleiner Perkins Caufield & Byers; and a fifth one, General Catalyst, is based in Palo Alto.
Social distancing wearables
Using smartphone-based apps to monitor social distancing obviously requires that all people carry a smartphone. When this is not possible, social distancing can be monitored by ad-hoc wearables that activate an alarm when two people get too close to one another. At least three such devices have already been developed in Europe. Kinexon (Munich, Germany) offers a wearable called SafeZone, based on a UWB (ultra wideband) sensor, that can be worn as a wristband or attached to clothing. Also based on UWB is the device developed by Belgian company Lopos, an Imec spinoff, in collaboration with Ghent university. Called SafeDistance, it enables an accurate (< 15cm error margin) distance measurement. SafeDistance will be available for sale starting 27th of May. The wearable developed by IIT (Istituto Italiano di Tecnologia, Genoa, Italy) is a wristband called iFeel-You that uses a radio signal on the Bluetooth frequencies to monitor the motion of the human body and the distance from another wristband. The device – currently a prototype, not available for sale – also sends an alert when the body temperature is higher than 37.5 degrees.
Using L-band for 5G and IoT services
The US Federal Communications Commission (FCC) has approved with conditions the application from Ligado – a company based in Reston, VA – to deploy a low-power terrestrial nationwide network in the L-Band that would primarily support 5G and Internet of Things services. Authorization has been granted after an extensive technical analysis to ensure that adjacent band operations – including the Global Positioning System (GPS), also using the L band – are protected from harmful interference. L-band is the range of frequencies from 1 to 2 gigahertz.
This week, EDACafe catches up on some of the news from the last thirty days – after four weekly articles devoted to specific topics: in particular, make sure to check out our special report on high-speed PCB design featuring interviews with Wade Smith (Ansys), Stephen Slater (Keysight), and Yuriy Shlepnev (Simberian). Let’s now move to some news, starting with an update on the upcoming Design Automation Conference: this year’s DAC will be held as a virtual event, scheduled for July 19 to 23.
Startups get zero-cost Arm IP
Early-stage silicon startups with up to $5m in funding can now take advantage of Arm’s “Flexible Access for Startups” program, granting them zero-cost access to IP from the Arm Cortex-A, -R and -M processor families, select Arm Mali GPUs, ISPs, and other foundational SoC building blocks. Startups will also be able to access Arm’s ecosystem of silicon designers, software developers, support, training and tools. Arm also announced a strategic partnership with Silicon Catalyst, an incubator focused exclusively on helping startups accelerate silicon solutions.
Arm-powered Macs?
Definitely not a startup, Apple also could be using more Arm IP in the future. The Cupertino giant is reportedly planning to start selling Mac computers with its own main processors by next year, relying on designs that helped popularize the iPhone and iPad. The future Arm-based Mac chips – which would replace the current Intel processors – will be reportedly manufactured by TSMC in a 5-nanometer process. Macs will still run the macOS operating system, rather than the iOS.
New Intel and AMD processors
And speaking of Intel, the recently announced 10th Gen Core S-series desktop processor family includes what the company claims to be “the world’s fastest gaming processor”. Dubbed Core i9-10900K, the chip can reach up to a maximum of 5.3 GHz thanks to Thermal Velocity Boost, a feature that opportunistically and automatically increases clock frequency based on how much the processor is operating below its maximum temperature. It also offers per-core hyperthreading control, allowing experienced “overclockers” to decide which threads to turn on or off on a per-core basis. Rival AMD, for its part, has announced global availability of “the world’s first x86 7nm commercial notebook processors,” the AMD Ryzen PRO 4000 Series Mobile family. The new series includes AMD Ryzen 7 PRO 4750U, that the company claims to be “the fastest business processor for ultra-thin business notebooks,” with up to 8 cores and 16 threads.
Image credit: Intel Corporation
Chinese “disruptive” flash memory chip
TechInsights, a Canadian reverse engineering firm, has recently analyzed the 64L 3D Xtacking NAND devices manufactured by Yangtze Memory Technologies Co. (YMTC), China’s first mass producer of 3D NAND flash memory chips. According to TechInsights, “There is no question that this will disrupt the 52 billion dollar NAND memory market and its respective market leaders.” Due to the Xtacking architecture in which periphery circuits and memory cell operations are processed on a separate wafer, the array efficiency and memory bit density of the YMTC device are considerably higher than conventional 3D NAND. TechInsights confirmed that YMTC’s Xtacking architecture uses two different dies for logic and memory array and employs some unique and very innovative technologies. According to TechInsights, this 64L 3D NAND flash device represents the first major competitive semiconductor product to come out of China’s state-backed investment in cutting-edge memory chips, part of the “Made in China 2025” initiative unveiled three years ago.
YMTC’s Xtacking architecture. Image credit: YMTC
More RF spectrum for Wi-Fi 6
The FCC (US Federal Communications Commission) has made 1,200 megahertz of spectrum in the 6 GHz band (5.925–7.125 GHz) available for unlicensed use. According to FCC, these new rules will usher in Wi-Fi 6, the next generation of Wi-Fi, and play a major role in the growth of the Internet of Things.
Belgian research institute Imec has presented the world’s first chip that processes radar signals using a spiking recurrent neural network (SNN). According to Imec, the neuromorphic device consumes 100 times less power than traditional implementations while featuring a tenfold reduction in latency. Its first use-case will be a low-power, anti-collision radar system for drones that can react much more effectively to approaching objects.
Imec’s neuromorphic chip. Image credit: Imec
Smartphones get advanced video technologies
A quick look at some recent announcements confirms the current role of smartphones as advanced video platforms. OmniVision has announced the OV64B, a 64-megapixel image sensor with a 0.7 micron pixel size, enabling 64 MP resolution in a 1/2″ optical format for the first time. This allows high-end and high mainstream smartphone designers to create the thinnest possible phones with high resolution 64 MP cameras. This sensor provides 4K video recordings with electronic image stabilization, as well as 8K video at 30 frames per second. MediaTek will enable YouTube video streams using the cutting-edge AV1 video codec on the MediaTek Dimensity 1000 smartphone SoC. And the fifth generation Pixelworks visual processor enables some OnePlus smartphone models to offer features such as upconversion of video dynamic range from standard (SDR) to high (HDR), automatic adaptation of the color tone of the display to match the color temperature of the ambient light, true-to-life skin tones, etc.
Acquisitions
Nvidia has recently completed its acquisition of Mellanox for a transaction value of $7 billion. The deal obviously targets datacenters and high-performance computing. Intelhas acquired Moovit, an Israel-based company offering Mobility-as-a-Service (MaaS) solutions. Upon close, Moovit will join Mobileye, the ADAS company that Intel acquired in 2017. Moovit combines information from public transit operators and authorities with live information from the user community to offer travelers a real-time picture of the best route for their journey. MaxLinear– a provider of ICs for the connected home, wired and wireless infrastructure – has entered into a definitive agreement to acquire Intel’s Home Gateway Platform Division, which comprises Wi-Fi access points, Ethernet and home gateway SoC products. New Wave Design and Verification, a provider of high-performance digital electronic interface solutions for the defense/aerospace market, has acquired FlightWire Technology, a provider of 1394b AS5643 (MIL-1394) solutions.
Artificial intelligence chips continue to be the hottest topic in the processor arena – as testified by the 2020 spring edition of the Linley Processor Conference, organized by the technology analysis firm Linley Group. Due to the Covid-19 pandemic, this year the April event – usually taking place in Santa Clara, CA – was held in a virtual format, with speakers addressing a remote audience through live streaming video. Here is a quick overview of some of the presentations.
AI trends and issues: larger models, binary weights, difficult porting
The keynote speechfromLinley Gwennap, principal analyst of the Linley Group, offered an overview of the current trends in AI architectures. The size of AI models is growing quickly to improve accuracy: as an example, in 2014 ResNet-50 had 26 million parameters, while the recent Turing NLG (Microsoft’s Natural Language Generation model) has 17 billion parameters. This obviously calls for more powerful processors, and vendors are responding with a diverse range of architectures. Most of them follow one of these two approaches: many small cores, or a few big cores. Both have advantages and disadvantages: little cores are easier to design, to replicate and scale to multiple performance/power points, while big cores require less complex interconnect and simplify compiler/software design. Recent architectural trends also include a shift from systolic arrays to convolution-optimized architectures (examples include chips from Alibaba and Kneron), and the adoption of Binary Neural Networks (BNNs), where weights can only be zero or one. This approach greatly reduces power and storage space relative to INT8 weights, still achieving a good accuracy. BNN hardware is available from Lattice and XNOR.ai (now Apple). (more…)
