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 EDACafe Editorial

Archive for April, 2020

Simberian interview: signal integrity and power integrity challenges in high-speed PCB design

Friday, April 24th, 2020

EDACafe Special Report: Signal Integrity and Power Integrity Challenges in High-Speed PCB Design

Part Three – Interview with Yuriy Shlepnev, President of Simberian Inc.

Signal integrity and power integrity issues are becoming increasingly challenging for designers of high-speed PCBs required by next generation applications such as 5G and new semiconductor devices such as DDR5 memories. What are the key aspects that designers should consider? What are the capabilities of the tools offered by EDA vendors to address these issues? To answer these questions, EDACafe has interviewed experts from some of the major vendors in this specific market. For part three of our special report we submitted out questions to Altium, that has partnered with Simberian – a company specializing in electromagnetic signal integrity software – to address the increasing importance of high-speed design and the need for PI and SI simulation. As a result of this partnership, Simberian’s simulation capability is integrated in the latest versions of Altium Designer. Answering our question on behalf of Altium is Yuriy Shlepnev, president of Simberian.

EDACafe: Users of Altium Designer can leverage the capabilities of Simbeor, Simberian’s electromagnetic signal integrity software. What are the benefits of this solution?

Yuriy Shlepnev: New signal and power integrity challenges should be addressed during the layout of the board. Ideally, a board designed by a layout engineer should be immediately compliant with the new signal integrity requirements and power delivery constraints.  Such approach would eliminate needs for multiple tools, costly post-layout analysis and would shorten the design process. This can be achieved by embedding signal and power integrity tools into a layout tool.  Use of Simbeor signal integrity solvers to compute impedance for any type of PCB interconnect in Altium Designer, is the first step in building such an integrated solution. Opportunity to control trace impedance in the beginning of the design process cannot be underestimated.  Selection of materials and stackup structure are all affected by the PCB designers’ ability to achieve a target impedance, delay and losses in all critical interconnects. This can be done seamlessly in Altium Designer 20, with the user experience tailored for the layout engineers, combined with the accuracy of the extensively validated Simbeor solvers.

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Keysight interview: signal integrity and power integrity challenges in high-speed PCB design

Friday, April 17th, 2020

EDACafe Special Report: Signal Integrity and Power Integrity Challenges in High-Speed PCB Design

Part Two – Interview with Stephen Slater, Product Planning and Marketing Manager at Keysight Technologies

Signal integrity and power integrity issues are becoming increasingly challenging for designers of high-speed PCBs required by next generation applications – such as 5G – and new semiconductor devices – such as DDR5 memories. What are the key aspects that designers should consider? What are the capabilities of the tools offered by EDA vendors to address these issues? To answer these questions, EDACafe has interviewed experts from some of the major vendors in this specific market. Part two of our special report features an interview with Stephen Slater, product planning and marketing manager at Keysight Technologies. On occasion of the last DesignCon show, Keysight introduced what it claims to be “the world’s first design and test workflow solution that reduces product development time for Double-Data Rate Dynamic Random-Access Memory (DDR5 DRAM) systems.” This interview will therefore focus mainly on DDR5 and on Keysight’s PathWave solution.

Keysight’s DDR5 complete design and test solution. Reproduced with permission, courtesy of Keysight Technologies, Inc.

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Ansys interview: signal integrity and power integrity challenges in high-speed PCB design

Friday, April 10th, 2020

EDACafe Special Report: Signal Integrity and Power Integrity Challenges in High-Speed PCB Design

Part One – Interview with Wade Smith, Application Engineer Manager at Ansys

Signal integrity and power integrity issues are becoming increasingly challenging for designers of high-speed PCBs required by next generation applications – such as 5G – and new semiconductor devices – such as DDR5 memories. What are the key aspects that designers should consider? What are the capabilities of the tools offered by EDA vendors to address these issues? To answer these questions, EDACafe has interviewed experts from some of the major vendors in this specific market. Part one of our special report features an interview with Wade Smith, application engineer manager at Ansys.

EDACafe: In your view, what are the major signal integrity and power integrity challenges posed – in high-speed PCB design – by next generation applications such as 5G and by new semiconductor devices such as DDR5 memories? Can you provide practical examples of critical issues in next-generation PCB layout?

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Perceive’s AI processor; tactile sensors; Tbit/s on a twisted pair; FPGA acceleration of legacy programs

Friday, April 3rd, 2020

A new edge inference solutions company has been making news over the past few days, claiming an outstanding power efficiency. Other updates this week are mostly from research works in different areas.

AI edge processing at 55 TOPS/Watt

On March 31st Perceive Corporation emerged from stealth mode and debuted its first product, the Ergo edge inference processor. According to Perceive, Ergo delivers more than 4 sustained “GPU-equivalent” floating-point TOPS, with the ability to run heterogeneous, large neural networks simultaneously, and offering a power efficiency of more than 55 TOPS/Watt. For example, Ergo can run YOLOv3 at up to 246 frames per second (batch size =1) at 30 frames per second while consuming about 20 mW. The processor has a 7×7 mm package and requires no external RAM. Ergo targets applications such as video object detection, audio event detection, and speech recognition, in consumer devices such as security cameras, smart appliances, and mobile phones. Perceive also announced that Ergo has been selected by two major providers of smart connected camera and security products – one of them being Arlo – to integrate advanced neural network applications into future products. The Ergo chip and reference board are currently being sampled to leading customers; the company expects to be ready for mass production in the second quarter of 2020. Founded in 2018 and based in San Jose, CA, Perceive is a majority-owned subsidiary of Xperi Corporation, the company known for brands such as DTS, IMAX Enhanced, HD Radio, and Invensas.
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