Simberian interview: signal integrity and power integrity challenges in high-speed PCB design

EDACafe Special Report: Signal Integrity and Power Integrity Challenges in High-Speed PCB Design

Part Three – Interview with Yuriy Shlepnev, President of Simberian Inc.

Signal integrity and power integrity issues are becoming increasingly challenging for designers of high-speed PCBs required by next generation applications such as 5G and new semiconductor devices such as DDR5 memories. What are the key aspects that designers should consider? What are the capabilities of the tools offered by EDA vendors to address these issues? To answer these questions, EDACafe has interviewed experts from some of the major vendors in this specific market. For part three of our special report we submitted out questions to Altium, that has partnered with Simberian – a company specializing in electromagnetic signal integrity software – to address the increasing importance of high-speed design and the need for PI and SI simulation. As a result of this partnership, Simberian’s simulation capability is integrated in the latest versions of Altium Designer. Answering our question on behalf of Altium is Yuriy Shlepnev, president of Simberian.

EDACafe: Users of Altium Designer can leverage the capabilities of Simbeor, Simberian’s electromagnetic signal integrity software. What are the benefits of this solution?

Yuriy Shlepnev: New signal and power integrity challenges should be addressed during the layout of the board. Ideally, a board designed by a layout engineer should be immediately compliant with the new signal integrity requirements and power delivery constraints.  Such approach would eliminate needs for multiple tools, costly post-layout analysis and would shorten the design process. This can be achieved by embedding signal and power integrity tools into a layout tool.  Use of Simbeor signal integrity solvers to compute impedance for any type of PCB interconnect in Altium Designer, is the first step in building such an integrated solution. Opportunity to control trace impedance in the beginning of the design process cannot be underestimated.  Selection of materials and stackup structure are all affected by the PCB designers’ ability to achieve a target impedance, delay and losses in all critical interconnects. This can be done seamlessly in Altium Designer 20, with the user experience tailored for the layout engineers, combined with the accuracy of the extensively validated Simbeor solvers.

EDACafe: In your view, what are the major signal integrity and power integrity challenges posed – in high-speed PCB design – by next generation applications, such as 5G, and by new semiconductor devices, such as DDR5 memories? Can you provide practical examples of critical issues in next-generation PCB layout?

Yuriy Shlepnev: The trace impedance control is the most critical element of compliant interconnects. The other obstacles for design of the compliant interconnects are discontinuities (vias, pins) and coupling (leaks and crosstalk).  First challenge of signal and power integrity design is the ability to design the interconnects with minimal possible distortion of the signals. It means design of interconnects with minimization of thermal and reflection losses and minimization of leaks and coupling. This will require radical change in the approach to interconnect design in general.  The spectrum of digital signal in 5G or DDR5 systems is well in the range of the microwave frequency. At these frequencies, interconnects should be treated as the waveguiding structures, and designed as the waveguiding systems. This might sound scary, but we have to accept this reality in order to move forward.  There is growing interest in understanding of what is happening in interconnects at the microwave and millimeter wave (112 Gbps) frequencies – it was the subject of our tutorial with Vadim Heyfitch from Xilinx “Design Insights from Electromagnetic Analysis & Measurements of PCB & Packaging Interconnects Operating at 6- to 112-Gbps & Beyond” at the recent DesignCon 2020. We presented several practical cases in the tutorial that illustrated different critical issues and impact on design, such as the importance of accurate skin-effect onset modeling in micron-size chiplet interconnects, and the importance of via discontinuity minimization in packages.  The second challenge is the predictability of how the interconnects will behave. Interconnect simulation at microwave frequency bandwidth may have nothing to do with the reality – may not correlate with measurements. So far predictability is restricted by the capabilities of the software solvers and by manufacturing variations. The systematic analysis to measurement validation step is not always included into the design process, but it must be included to design predictable interconnects.

EDACafe: If not properly addressed, what impact could these challenges have on system performance, cost and time to market? Is “overdesign” a common problem today?

Yuriy Shlepnev: An interconnect system designed with non-validated EDA software and manufactured with unknown variations with materials that do not have proper broadband models may simply not work properly. It is practically impossible to figure out the reason “post mortem”. EDA vendors will assure you that their tools are accurate and work properly (usually showing anecdotal evidence) and manufacturers will assure you that the interconnects are manufactured as designed. None of that may be true and it is all “sink or swim” after that.  Considering overdesign, packaging and PCB interconnects are rather “under-designed”. Previous research work showed that the package was the weakest link in the interconnect system, and that to make it work, a chip must have very sophisticated, power hungry and costly signal conditioning circuits – CTLEs and DFEs. Building and using such circuits may be considered as chip “overdesign”. An alternative to avoid this, is to re-design the package and PCB as clean, low-loss waveguiding channels. Considering package and PCB interconnect bandwidth, we are very far from the fundamental limits. 

EDACafe: The EDA industry as a whole is developing new approaches to tackle the new signal integrity and power integrity challenges, such as SI/PI co-simulation and the adoption of IBIS-AMI models for DDR5 memories. In you view, what are the most promising approaches? How mature are them?

Yuriy Shlepnev: The “divide and conquer” strategy is a good approach when we are dealing with complex systems. In application to the interconnects it is called de-compositional electromagnetic analysis. The system is divided into structures that can be simulated separately as transmission lines (traces) and discontinuities (vias, pads, pins, connectors, packages).  Then, S-parameter models are built for each element with electromagnetic solvers and the models are united into S-parameter models of complete link – from chip to chip. Such an approach is fast, flexible and can be used for interconnect optimization (unlike the analysis as a whole). Such models can include cross-talk between vias and traces, but not effects of PDN. SI/PI co-simulation with PDN solves different problems of the power delivery or control of simultaneous switching noise. Models for signal distribution nets analysis require much higher bandwidth comparing to the models for the power distribution nets.  Models used in SI/PI co-simulations do not have accuracy at the bandwidth of even DDR5 signals. On the other hand, 3D EM models are needed for vias and discontinuities at the microwave bandwidth for analysis of vias in DDR5 signal nets. Building such models is possible only in the isolation from the rest of the PCB or package – if the discontinuity is electrically localized by design. This is a simple concept, but it requires a change of perspective on all interconnect design processes adopted for the lower data rate designs.  All transitions must be designed with the power flow localization as the main condition (reduction of sensitivity to manufacturing variations is the second condition). You can watch “How interconnects work” video series on the Simbeor YouTube channel. One can think about it like that – interconnects are channeling signal energy as pipes (actually, waveguides), but some of their elements can violate the localization (think vias without stitching or improper stitching) and leak the energy. Most of DDR3 and DDR4 interconnect designs will become such leaky pipes at data rates of GDDR5 and GDDR6. The problem can be eliminated if routing software would not allow the “leaky pipes”. Software that is based on use of structures that have conditionally localized models (controlled coupling) with the impedance and loss control – no additional analysis would be required. I call it model-driven routing.  Considering the system-level analysis of interconnects, I think that Channel Operating Margin (COM) is the most promising approach for the package and PCB designers. It is sufficiently accurate and very simple approach extensively used up to 112 Gbps by Ethernet group and some other standard committees. It is also the alternative to the IBIS-AMI.  Another very promising approach is use of machine learning algorithms as we demonstrated with Alex Manukovsky’s group from Intel at the recent DesignCon 2020. It is chip-to-chip pre-layout system investigation to define the ranges for each important design variable (dielectric, impedance, separation, etc.) with the goal to maximize the likelihood metrics for proper data transmission. It is a very promising alternative to sweeps and rule-based design.

EDACafe: Several major EDA vendors, such as your company, are already offering solutions addressing the new signal integrity and power integrity challenges. How can users choose the best solution? What features should they be looking for, when choosing a new EDA platform for this kind of application?

Yuriy Shlepnev: Accuracy over the signal bandwidth is always the first priority. The tool must be systematically validated with the repeatable process. For instance, GDDR5 is over 10 Gbps per one link – tools must have bandwidth and validated to at least 20 GHz. Validation up to 50 GHz is required for the leading-edge data rates 28 Gbps NRZ of 56 Gbps PAM4.  The number of EDA tools that can pass such validation is actually very small. The second feature to look for is the ease of use. The learning curve for some electromagnetic tools may be very steep and require a PhD in electromagnetics to use.  And of course, software costs – electromagnetic tools to design predictable interconnects should not cost an arm and a leg.

EDACafe: Can you briefly describe your company’s offering in this space, including the suggested design flow? Can you highlight the features and benefits that set your solution apart from the others?

Yuriy Shlepnev: At Simberian, we develop Simbeor electromagnetic signal integrity software to design predictable PCB and packaging interconnects. It is based on the decompositional electromagnetic analysis approach. The accuracy of the solvers is proven with independent and repeatable validation.  Altium Designer software uses Simbeor SDK to build Stackup Manager to enable layout engineers to design the impedance-controlled interconnects with high confidence. This is the first step toward the model-driven routing with the signal integrity problems solved simultaneously with the board layout. Our solvers and tools are the key components in that solution.  To support the analysis to measurement validation, Simbeor provides four techniques for material model extraction – based on GMS-parameters, SPP technique (originally developed at IBM), SPP Light and Gamma-T techniques developed in collaboration with Chris Cheng group from HPE. Simbeor includes tools to evaluate the quality of S-parameter models of connectors or cables. It includes everything to create chip-to-chip interconnect model prototype and optimize all transitions in a pre-layout stage in general to minimize reflections. In particular, it has tools for the localization-aware pre-layout design of non-reflective viaholes. Also, Simbeor includes tools for automatic post-layout decompositional electromagnetic analysis.  Both pre and post-layout electromagnetic analysis can be effectively accelerated with distributed computing in a local network or in a cloud (AWS for instance). Very easy to setup and use and cost-effective, comparing to all competitors. All Simbeor solvers, material identification and pre-layout tools are now available in form of DLLs with API in C/Matlab and Python for signal integrity analysis automation. It allows automation of analysis of tens of thousands of cases to feed the feature range analysis algorithm and do either root cause analysis or identify the ranges with maximal likelihood of success.

This concludes Part Three of our special report on signal integrity and power integrity challenges in high-speed PCB design – the interview with Yuriy Shlepnev, president of Simberian Inc.

Related articles:

Interview with Wade Smith, application engineer manager at Ansys (Part One of this special report)

Interview with Stephen Slater, product planning and marketing manager at Keysight Technologies (Part Two of this special report)

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