Recent announcements from Cadence and Synopsys testify that concurrent satisfaction of multiple constraints is a key challenge for today’s chip design. More news this week concern advancements in Intel’s neuromorphic initiative, a research work on IoT cross-technology wireless communication, IC market data, and an event update.
New Cadence digital full flow
The new release of the Cadence digital full flow has been enhanced to further optimize power, performance and area results. One of the enabling innovations to this goal is what Cadence has dubbed “iSpatial technology”, which integrates the Innovus Implementation System’s GigaPlace Placement Engine and the GigaOpt Optimizer into the Genus Synthesis Solution. As Cadence explained in a press release, the iSpatial technology allows a seamless transition from Genus physical synthesis to Innovus implementation using a common user interface and database. Other enhancements include the addition of machine learning capabilities, that enable users to leverage their existing designs to train the new optimization technology to minimize design margins; and lastly unified implementation, timing- and IR-signoff engines. Engine unification enhances signoff convergence by concurrently closing the design for all physical, timing and reliability targets. According to Cadence, this allows customers to reduce design margins and iterations.
The new Cadence digital full flow. Image credit: Cadence
Synopsys shifts left RTL closure
Synopsys has introduced RTL Architect, a product aiming to “shift left” (move to an earlier phase in the design flow) the RTL design closure. According to the company, RTL Architect is the industry’s first “physically aware RTL design system”, which reduces the SoC implementation cycle in half and delivers superior quality-of-results (QoR). This is obtained through a fast, multi-dimensional implementation prediction engine that enables RTL designers to predict the power, performance, area, and congestion impact of their RTL changes. The RTL Architect system is built on a unified data model that provides multi-billion gate capacity and comprehensive hierarchical design capabilities. Synopsys’ PrimePower golden signoff power analysis engine is directly integrated with the new product.
Intel’s neuromorphic system reaches 100 million neurons
Intel has recently announced the readiness of Pohoiki Springs, its latest and most powerful neuromorphic research system providing the computational capacity of 100 million neurons – the size of a small mammal brain. Pohoiki Springs, a data center rack-mounted system, integrates 768 Loihi neuromorphic research chips inside a chassis the size of five standard servers. The cloud-based system will be made available to members of the Intel Neuromorphic Research Community (INRC).
Intel’s Pohoiki Springs. Image credit: Intel Corporation
Another recent advancement concerning Loihi is a research demonstrating its ability to “smell” and recognize ten hazardous chemicals. Training was carried out using a dataset from an array of 72 sensors detecting chemicals in the air. The research, jointly carried out by Intel Labs and Cornell University, demonstrated that Loihi is particularly efficient in this task, even in the presence of significant noise and occlusion: the chip learned each “odor” with just a single sample, without disrupting its memory of previously learned scents, and showed superior recognition accuracy compared with conventional state-of-the-art methods. Key to these performances is a neural algorithm derived from the architecture and dynamics of the brain’s olfactory circuits.
Energy bursts connect different wireless standards in IoT devices
Researchers at TU Graz (Graz University of Technology, based in Graz, Austria) have developed a solution that enables direct information exchange between commercially available IoT devices that use different wireless technologies (Wi-Fi, Bluetooth, ZigBee) but the same radio frequencies. Called X-Burst, the solution is based on the wireless transmission and reception of energy pulses (energy bursts) and leverages the ability of most IoT devices to generate and detect such pulses, irrespective of the wireless standard they use. Bursts contain data packets of varying lengths, where the information is encoded in the duration of the packets. The receivers monitor the energy level in the radio channel and can thus detect the packets, determine their duration and finally extract the information they contain. According to the research team, the solution enables communication between different wireless technologies without the need for expensive and inflexible gateways. The researchers concentrated primarily on data exchange in the license-free 2.4 GHz band. The solution also enables the system clocks of the various devices to be synchronized, allowing action coordination, and negotiation of radio frequencies to minimize cross-technology interference.
U.S. IC companies maintained global market share lead in 2019
According to a report from market research firm IC Insights, 2019 regional market shares of IDMs (companies operating wafer fabs), fabless companies, and total IC sales were led by U.S. headquartered companies. U.S. companies held 55% of the total worldwide IC market in 2019 followed by the South Korean companies with a 21% share, down six percentage points from 2018. Taiwanese companies, on the strength of their fabless company IC sales, held 6% of total IC sales, one point less than the European companies. As highlighted by the report, South Korean and Japanese companies have an extremely weak presence in the fabless IC segment and the Taiwanese and Chinese companies have a noticeably low share of the IDM portion of the IC market. Overall, U.S.-headquartered companies showed the best-balanced combination of IDM, fabless, and total IC industry market share. The report also provides year-on-year (2019 versus 2018) sales growth data on a regional basis. This part of the research shows that the South Korean-headquartered companies – primarily Samsung and SK Hynix – registered a 32% sales drop, the worst of any major country/region. This was driven by a collapse in DRAM and NAND flash memory IC sales in 2019.
Linley Spring Processor Conference goes virtual
The upcoming Linley Spring Processor Conference, scheduled for early April in Santa Clara, CA, will be held as a virtual event. Attendees connected through the Internet will be able to view live-streamed presentations and interact with the speakers during Q&A and breakout sessions. The virtual conference will be online from April 6th to 9th, morning only (from 9:00 am to 1:00 pm PDT). Topics will include AI for ultra-low-power applications; 5G and AI at the network edge; datacenter processors and accelerators; AI for embedded application; processor technology.
