A closer look at Empyrean Software

Following our recent video interview to Jason Xing – President and CEO, North America, at Empyrean – let’s now take a closer look at Empyrean Software and its product offering. But first, a couple of words about this company headquartered in Beijing, with offices in San Jose, CA. Founded in 2009, Empyrean Software is the largest EDA software provider in China, and its R&D team has more than 30 years of experience in technology and product development. The company has comprehensive cooperation with many corporations, universities and research laboratories. As posted in the company’s website (www.empyrean-tech.com), publicly disclosed Empyrean customers include Renesas, Diodes Incorporated, Monolithic Power Systems and Ricoh.

New addition: Polas, a reliability analysis tool for power ICs

Let’s start with the latest addition to Empyrean’s AMS product line: Polas, a reliability analysis tool for power ICs. Polas provides comprehensive capabilities such as Rds(on) calculation, EM/IR-drop analysis, power MOSFET timing analysis, crosstalk analysis, and reliability rule checking. It is an effective, one-stop solution for power IC designs. According to Empyrean, the traditional RC extraction method cannot meet the needs of power IC designers; Polas, instead, allows engineers to sign off and safeguard the quality of their designs.

A superfast SPICE simulator with optional GPU acceleration

One of the most important products in the Empyrean product offering is ALPS, a fast, high-capacity parallel SPICE simulator that can simulate designs with up to 10 million elements. According to Empyrean, ALPS delivers SPICE-level accuracy with excellent performance and capacity for the most challenging analog and mixed-signal designs. Compared to traditional SPICE tools, ALPS offers a significant performance speedup thanks to its advanced parallel technique. For post-layout simulation, it delivers a breakthrough technology dubbed SMS (smart matrix solver, patent pending) that significantly improves performance without accuracy loss. An element in Empyrean’s complete analog and mixed-signal flow, ALPS works seamlessly with leading custom design platforms. And Empyrean has recently introduced the possibility of running ALPS with a GPU accelerator, allowing for a 2x to 5x speed boost over the software-only solution.

A comprehensive design closure solution for SoCs

One of the major themes on which Empyrean is focused is design closure for advanced SoCs with hundreds of clocks and dozens of power domains. The goal is to reduce the number of iterations required to achieve closure, thus making it easier for design teams to meet their time to market constraints. Empyrean addresses this problem with three products – ClockExplorer, Empyrean-XTime, and Empyrean-XTop – that together make up a comprehensive design closure solution. ClockExplorer provides a platform for both front-end and back-end teams involved in designing clock trees. It offers a comprehensive clock check within a KPI (Key Performance Indicator) system, which help designers review the clock structure, ensuring and improving the CTS quality. Empyrean-XTime addresses the needs of advanced designs below 16nm and IOT applications: low yield due to inaccurate timing, too much power and area cost due to extra margin. Key features of the tool include timing paths SPICE signoff, fast Monte Carlo critical path analysis, design margin recovery, V/T sweeping for low power limitation and sensitivity analysis. The tool improves design PPA and yield, and pinpoints design bottlenecks with advanced big data analysis. Empyrean-XTop is a placement- and routing-aware, multi-corner, multi-mode timing ECO solution with minimal impact to power and area in nanometer-scale IC designs, addressing designs with 100M+ instances, 300+ scenarios, and 100+ critical paths. It helps design teams to achieve faster timing/ECO closure and complements existing place and route and sign-off STA (Static Timing Analysis) tools in a user’s flow. Key features of Empyrean-XTop include simultaneous and fast MMMC timing fixing on signal and clock paths; fixing of setup, hold, max transition/capacitance and SI violations, etc. It can be added in a plug-and-play mode to existing flows using standard interfaces.

More Empyrean tools

Other key Empyrean products include Skipper, Aether, Argus, and RCExplorer.

Skipper is a high-performance chip finishing tool capable of efficiently handling today’s largest layout databases (over 100GB GDS). It enhances designer productivity and accelerates tape-out. Thanks to its built-in applications, the tool offers a number of features including merging standard cells and IPs, layout editing, hierarchical delete, net tracing, Boolean operations, seal-ring sizing, debugging DRC/LVS results, preparing FIB data for device analysis etc. Skipper allows fast full-chip layout comparison between different layout format (FlashLVL) and offers a unique “layout server” mode to share layout data.

Aether is a schematic and layout design platform for custom IC designs using OpenAccess as the native database. This platform has several built-in modules such as design manager (Aether-DM), technology manager (Aether-TM), schematic editor (Aether-SE), layout editor (Aether-LE), schematic-driven layout (Aether-SDL), mixed-signal simulation environment (Aether-MDE), etc. It features PyCell-based schematic-driven layout, and fits into industry-standard analog and mixed-signal flows.

Argus is a fast and accurate in-design DRC/LVS solution for analog, digital and mixed-signal designs. Its multi-threaded architecture is used to process commands and data in parallel and – according to Empyrean – makes it one of the highest performing DRC/LVS tools. Its key features include high performance dimensional, density and antenna checking; user-selectable region-based DRC; and an integrated debug environment. Easy to learn, the tool works with GDSII, OASIS and OpenAccess.

RCExplorer offers fast, in-design, pre-LVS and post-extraction parasitic analysis. This includes DSPF/SPEF-based pin-to-pin and point-to-point analyses. Also supported is interactive, layout-based point-to-point interconnect parasitic analysis. It handles large RC networks like power mesh. According to Empyrean, the tool shortens design cycles and reduces post-extraction parasitic analysis from days to minutes.

Checking library quality

Among the products that differentiate Empyrean’s offering is Qualib, a library/IP quality assurance and debugging platform. Qualib aims at checking the consistency of all kinds of library files, assuring the functionalities for debugging, cross-reference and reports generation. Currently, Qualib supports multiple formats including LEF, GDS, Timing Lib, Verilog and CDL. Benefits for IP users include the possibility to find tape-out showstoppers earlier in the design cycle, thus reducing the risk of missing tape-out schedule. Qualib can also be used by IP creators, allowing them to provide high quality IPs that customers can trust. Easy to use, Qualib provides both graphic and TCL based user interface.

And speaking of IP, Empyrean is also present in this market with its own offering, specializing in analog IP and fast SerDes IP. Foundries supported by the company are TSMC, UMC, SMIC, and HLMC, and the Empyrean AMS design platform is supported by TowerJazz. Lastly, Empyrean offers IC design services and a full design flow platform for Flat Panel Displays.

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