Archive for the ‘Uncategorized’ Category
Thursday, October 20th, 2022
The Electronic System Design (ESD) industry continues to post strong revenue numbers and project a positive future for the close to 55,000 people employed in our ecosystem. Just consider, the ESD industry reported the highest year-over-year increase in more than 10 years with quarterly revenue reaching a record $3,748.7 million. In fact, revenue increased 17.5% from $3,191.4 million in Q2 2021 to $3,748.7 million in Q2 2022 and the four-quarter moving average, which compares the most recent four quarters to the prior four, rose 15.3%. All product categories and geographic regions recorded growth in the quarter.
These numbers were stated by us –– the ESD Alliance, a SEMI Technology Community –– in our latest Electronic Design Market Data (EDMD) report. As for companies tracked by the EDMD, they employed 54,408 people globally in Q2 2022, an 8.9% increase over the Q2 2021 headcount of 49,964 and up 6% compared to Q1 2022. (more…)
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Wednesday, October 12th, 2022
I’m pleased to welcome Axiomise of London and Silicon Assurance from Gainesville, Florida, to the ESD Alliance of SEMI. It’s great to see small and emerging companies like Axiomise and Silicon Assurance in our design ecosystem to help ensure its vibrancy and innovation.
Follow me as I offer thumbnail sketches of both.
Getting to Know Axiomise
www.axiomise.com (PRNewsfoto/Axiomise Ltd.)
Verification is an increasingly critical part of system design and Axiomise plays a significant role as a leading provider of cutting-edge formal verification training and services along with specialized verification solutions for RISC-V. It was founded by CEO Dr. Ashish Darbari about five years ago and since then, Axiomise engineers trained more than 200 verification engineers and offered countless solutions to semiconductor companies worldwide.
Ashish himself is an impressive figure as a noted formal verification practitioner of more than 20 years who continues to regularly use the entire toolbox of formal technologies, including theorem proving, model checking and equivalence checking. He also boasts 47 formal verification patents.
When asked why Axiomise joined the ESD Alliance and SEMI, Ashish was quick to answer: “It’s important for companies of our size to be part of the thriving electronic system design community. The networking and educational events and technical programs offer us a platform to reinforce the value of formal verification in semiconductor design in the global electronics industry.”
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Wednesday, October 5th, 2022
In so many ways, Mark Templeton was a giant in the semiconductor industry. At the time of his death in 2016, Mark was a prominent and highly respected Silicon Valley venture capitalist who leveraged his engineering background to foster scientific advancement.
That’s why it’s fitting that he was inducted posthumously this week into the Phil Kaufman Hall of Fame, co-sponsored by the ESD Alliance of SEMI and the IEEE CEDA. The honor recognizes Mark’s significant and innovative contributions to the electronic system design industry.
Mark leaves a legacy of technical and business innovation and that creativity endures after his untimely death. As a director and board member of numerous technology companies, he was instrumental in driving semiconductor IP market growth by spearheading technical innovations and developing new business models. For example, Mark co-founded Artisan Components Physical IP in 1991, where he served as president and CEO. Under his leadership, Artisan Components quickly set the industry standard for implementing complex SoC designs.
“Often overlooked is Mark’s genius,” remarks Lucio Lanza, managing director of Lanza techVentures, who nominated Mark for the recognition. “He created a new and innovative business model for silicon IP, moving away from upfront fees to a success-based approach.” In fact, Artisan was the first company to offer free custom IP blocks for semiconductor design and was compensated once the design was completed, a model that has promoted design community growth. Tens of thousands of chip designs using custom IP blocks have since been implemented, spanning 15 different process technologies and 18 foundries. Artisan went public in 1997 and was acquired by Arm in 2004. From 2004 to 2006, Mark was president and Chief Strategy Office of Arm North America and also served on the Arm Holdings board of directors.
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Thursday, September 29th, 2022
It gives me great pleasure to announce Dr.Giovanni (Nanni) De Micheli is the recipient of the 2022 Phil Kaufman Award for Distinguished Contributions to Electronic System Design presented annually by the ESD Alliance of SEMI and IEEE CEDA.
Nanni, Professor and Director of the Institute of Electrical Engineering and the Integrated Systems Centre at EPFL in Lausanne, Switzerland, is being honored for his extensive contributions to EDA. His research in EDA tools and methodologies has advanced the academic field and made an impact on industry designs through their use in commercial EDA tools and design methodologies.
According to his nominators, Nanni created multiple technologies and inspired his students and researchers at universities as well as engineers in industry. His work has expanded the fields of high-level synthesis, logic synthesis, and networks on chips for more than 30 years.
“Professor De Micheli, or Nanni to many of us, who’ve been driving our industry forward for decades, stands as a relentless advocate for our field,” remarks Aart de Geus, Chairman and CEO of Synopsys and a member of the ESD Alliance Governing Council. “I am not alone when I express my appreciation to Nanni for advancing the field, but most important, for continuing to add findings that keep our profession fresh and exciting!”
The award ceremony and dinner will be held in early 2023. We hope you will join the ESD Alliance, its Governing Council and IEEE CEDA in honoring Nanni at the award dinner. Registration information will be available soon.
The news release offers a full look at Nanni’s contributions to our industry.
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Thursday, September 22nd, 2022
The ESD Alliance and its Governing Council mourns the death of Phil Moorby, 2005 Phil Kaufman Kaufman Award recipient for his efforts in the development of the Verilog language and its associated family of simulators.
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Monday, September 12th, 2022
Note: Below is my most recent Q&A blog post with Charles Shi from Needham & Company that appears on the SEMI website.
Charles Shi, Principal, Senior Analyst, Needham & Company, LLC., recently offered an upbeat assessment of the electronic design automation (EDA), silicon intellectual property (IP) and services industry, or what SEMI refers to as the electronic system design (ESD) ecosystem. I attended his presentation during the 2022 Design Automation Conference, collocated this year with SEMICON West and found it fascinating.
His presentation, titled EDA Powers Through Semiconductor Cycles, is well worth taking the time to read.
Smith: You are optimistic that EDA will be okay through a downcycle, according to your recent presentation. Even so, are there steps companies can or should take to be prepared?
Shi: I do think EDA will continue to grow through a semiconductor downturn. R&D is the last place for semiconductor companies to cut costs as they do not want to miss the upturn, which will eventually come, by pausing new chip R&D during a downturn. However, the range of possibilities of the upcoming downturn is wider than the previous downturns.
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Thursday, September 1st, 2022
Summer’s almost over, school’s back in session and it’s time to look forward. It’s an even better time to join the ESD Alliance, a SEMI Technology Community. The reasons for joining are numerous.
Much of the ESD Alliance member value is derived from the various technical- and business-focused committees. With committee membership consisting of subject matter experts in our member companies, these groups address key areas of common concern for our industry.
One such area is the quarterly SEMI Electronic Design Market Data (EDMD) report, a resource that is part of the Market Information initiative. Public and private EDA, semiconductor IP and services companies provide detailed revenue data in confidence to an independent auditing firm. The aggregated data is reported by detailed product categories and geographic regions on a quarterly basis. Each report includes tables and graphs with current and recent revenue and employment trends by quarter, allowing companies to review trends affecting their specific product segments.
The increasingly important Risk Management initiative includes SEMI’s Washington, D.C. policy and advocacy office, representing all member companies with a unified voice on export licensing and compliance issues. We also help to train future government leaders in the semiconductor design ecosystem to enable more educated future decisions affecting the industry.
The License Management and Anti-Piracy Committee reviews third-party licensing management software used by member companies for issues, updates and best practices. A significant ongoing effort is the SEMI Server Certification Protocol (SSCP), a years-long joint development effort led by the ESD Alliance with committee members Cadence, Siemens EDA and Synopsys (see my previous blog post for details). The SSCP addresses software piracy by providing a means to assure that licenses are issued only by authorized servers, reducing software piracy and benefitting both software vendors and customers.
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Thursday, August 25th, 2022
Here’s another in my series of Q&A interviews with member companies that appeared earlier this year on the SEMI website. In this post, I talked with Methodics founder and CEO Simon Butler, now general manager of the Methodics Business unit at Perforce, a member of the ESD Alliance, a SEMI Technology Community.
Product lifecycle management is a well-adopted methodology used in mechanical design. Until recently, it was not widely used in the semiconductor industry. That all changed when Methodics created intellectual property lifecycle management or IPLM, a design-centric mechanism for tracking and analysis of semiconductor IP and design. The result is a workspace for chip designers who often reuse existing IP.
Methodics was acquired by Perforce in 2020 and continues its quest to complete the digital thread, a traceable system from product definition and requirements all the way through semiconductor development.
Methodics founder and CEO Simon Butler is now general manager of the Methodics Business unit at Perforce, a member of the ESD Alliance, a SEMI Technology Community. Simon and I recently discussed the Methodics by Perforce survey of semiconductor design professionals that identified challenges, trends and opportunities in 2022. What follows is a condensed version of our discussion.
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Tuesday, August 9th, 2022
Over the past three years, the ESD Alliance’s License Management and Anti-Piracy (LMA) Committee has worked with member companies Cadence, Siemens EDA and Synopsys to develop a protocol for use with software license management systems to provide strong protection against piracy by defining how servers can be uniquely identified.
Sashi Subramanian, senior group director at Cadence, chairs the LMA and leads the development of the SEMI Server Certification Protocol. In my recent conversation with Sashi, we discuss the driving factors behind the creation of this new protocol, the challenges of bringing it to market and a status update.
Smith: What is a server certification protocol? What is its purpose?
Subramanian: The protocol is a means by which compute servers that run license server software can be uniquely identified. The purpose is to thwart software piracy that relies on cloning server identifications by allowing only entitled instances of license server software to run.
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Thursday, August 4th, 2022
Note: Below is a Q&A post I did initially for SEMI’s blog with Thiago Figueiro, vice president of Sales, Marketing and Business Development at Aselta. Aselta produces software for wafer and mask patterning based on e-beam technology for IC manufacturing, along with advanced metrology solutions for scanning electron microscopes. Our wide-ranging conversation covered trends and improvements in semiconductor manufacturing, supply chain challenges and the startup experience in France.
Aselta Nanographics of Grenoble, France, which produces software for wafer and mask patterning based on e-beam technology for IC manufacturing, along with advanced metrology solutions for scanning electron microscopes, recently became an ESD Alliance member. Adding to its impressive credentials, Aselta is a spin-off of CEA-Leti, the electronics and information technologies research institute also in Grenoble.
The increasing complexity of IC manufacturing poses a number of challenges including the mask data preparation required to enable technology improvements such as multi-beam (MB) mask writers and extreme ultraviolet (EUV) lithography. Measuring and inspecting the effects both on reticle and on wafer are also challenging.
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