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 Bridging the Frontier

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ESD Alliance Elects 10-Member Governing Council, Including Executives from Ansys, Keysight

Wednesday, May 10th, 2023

The election results are in and it’s a pleasure to announce the ESD Alliance’s incoming Governing Council for the 2023-2025 term, a mix of returning council members and two new members.

We’re adding Niels Faché, vice president and general manager of Keysight, and John Lee, general manager and vice president of Ansys, as our two new members. Outgoing members are Dean Drako of IC Manage and Simon Segars. I would like to personally thank Dean and Simon for their many years of service to the ESD Alliance and their commitment to the industry.
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Electronic System Design Industry Logs $3.8 Billion in Revenue in Q4 2022, CEO Outlook May 18

Wednesday, May 3rd, 2023

Electronic System Design (ESD) industry revenue grew yet again, according to the latest Electronic Design Market Data (EDMD) report from the ESD Alliance, a SEMI Technology Community. ESD revenue increased 11.3% to $3,858.7 million in the fourth quarter of 2022, up from $3,468.2 million in the fourth quarter of 2021. The four-quarter moving average was 12.6%, a percentage based on comparisons for the most recent four quarters to the prior four.

The good news continues as all geographic regions recorded growth in the quarter with Asia Pacific (APAC)reporting a double-digit increase. APAC secured $1,397.5 million of ESD products and services in Q4 2022, a 17.9% increase growing the four-quarter moving average to 17.1%.
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A Notable Lineup for 2023 CEO Outlook May 18

Wednesday, April 19th, 2023

 

 

You won’t want to miss this year’s CEO Outlook hosted by the ESD Alliance and sponsored by Keysight! It will take place Thursday, May 18, in Santa Clara, Calif. We have a notable list of panelists and Ed Sperling, editor in chief of Semiconductor Engineering, will moderate and lead the discussion about the current state and future of the chip design and semiconductor industries.

Our panelists are:

  • Dean Drako, President and CEO of IC Manage
  • Niels Faché, VP and GM at Keysight EDA
  • John Kibarian, President and CEO of PDF Solutions
  • John Lee, GM and VP at Ansys
  • Prakash Narain, President and CEO of Real Intent
  • Joe Sawicki, Executive Vice President of Siemens EDA
  • Simon Segars, Chair, ESD Alliance Governing Council

As always, we encourage audience participation and feedback, so join us and bring your questions and observations.
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Mark the Calendar: 2023 CEO Outlook May 18

Thursday, April 6th, 2023

 

Our yearly CEO Outlook will be held Thursday, May 18, in Santa Clara, Calif., with Ed Sperling, editor in chief of Semiconductor Engineering, serving as moderator. Ed will lead a panel discussion about the current state and future of the chip design and semiconductor industries. We’ll announce the panelist lineup soon.

The in-person event, co-sponsored by Keysight, will be held at Agilent’s Building 5 at 5301 Stevens Creek Blvd. in Santa Clara beginning at 5:30 p.m. with networking, food and beverages. The hour-long panel starts at 6:30 p.m. and is open to ESD Alliance and SEMI members at no cost. Pricing for non-members is $50 per person. Details and registration can be found at: https://bit.ly/3UbF1Lf

The ESD Alliance Annual Membership meeting for members will be held prior to the start of the CEO Outlook beginning at 5 p.m. Non-members with tickets to the CEO Outlook are welcome to sit in on the membership meeting.
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Rescheduled! Export Seminar on Impact of New Regulations on the Semiconductor Design Ecosystem

Wednesday, March 29th, 2023

Originally scheduled to be held in March, “The Impact of New Regulations on the Semiconductor Design Ecosystem,” was postponed due to scheduling conflicts to Wednesday, April 26, from 8:30-11am at Cadence’s corporate headquarters in San Jose, Calif.

The seminar, presented by SEMI’s ESD Alliance Export Committee, will be hosted by Ada Loo, chair of the ESD Export Committee and Cadence’s Group Director and Associate General Counsel. Attendees will learn why and how governments implement trade controls and what “exports” are and how they take place in different business contexts. Explanations will help clarify common due diligence methods, such as customer screening, that U.S. companies use to incorporate regulatory compliance into their business processes. The seminar also will focus on recent regulatory updates that address current issues including U.S.-China trade relations and the anticipated effects of those regulations on the US semiconductor design ecosystem.
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License Server Certification Task Force Formed

Tuesday, March 21st, 2023

The design and manufacture of today’s semiconductor chips is a complex process, requiring advanced software tools throughout the design to manufacturing flow. These tools require a team of talented engineers to develop and maintain. As the industry advances to smaller geometries and heterogeneous integration, new challenges arise requiring more research and development of the software used throughout the design ecosystem. These efforts are funded through the sale and licensing of the software.

One of the ongoing efforts of the Electronic System Design Alliance (ESD Alliance), a SEMI Technology Community, is the License Management and Anti-Piracy Committee (LMA). Part of the committee’s purpose is to help reduce the incidence of unauthorized use (piracy) of this complex software.  Unauthorized use negatively impacts both the tool vendors and customers. It deprives the software developers of revenue for their continuing efforts to develop new products that address the increasingly complex design ecosystem. Software piracy impacts the legitimate users of the software in two ways. First, the vendors may need to increase prices to be able to continue their R&D of new products and functionality. Second, it provides an unfair competitive advantage to those companies who are not paying for the software.
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An Epic Chiplet Evolution

Monday, March 13th, 2023

 

Chiplet evolution

Note: I recently talked with Jean-Marie Brunet, Vice President and General Manager of the Siemens Hardware-Assisted Verification business unit, about the growing use of chiplets. He has a unique perspective that’s captured below in a blog post I wrote for 3D InCites.

 

Jean-Marie Brunet, Vice President and General Manager of the Siemens Hardware-Assisted Verification business unit finds himself and his group in a unique situation when it comes to the topic of chiplets. The group designs a chiplet for their own products and sells those products to verification engineers who are verifying chiplet designs.

I recently had a conversation with Jean-Marie to get his perspective on chiplets and why he believes they are leading an epic chiplet evolution.

Smith: A significant challenge to chiplet adoption is scaling. Is that the biggest challenge or are there more pressing challenges?

Brunet: It’s a big topic. First, let me explain why. I manage an organization that develop hardware verification technology to the market –– emulators and FPGA prototyping hardware.

In the case of the emulator, we create all parts of the emulator. We build a very large device with a complex hardware architecture that must run a large amount of software. By developing our own hardware, we understand scaling challenges.

In terms of scaling, there is a lot of talk about how Moore’s Law is dead. No, Moore’s Law is doing just fine. Today semiconductor companies are designing for two or three nanometer process technology that uses a different type of transistor so it’s very expensive to go to an advanced node.
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Join Us for “The Impact of New Regulations on EDA and SIP” Export Seminar March 28

Tuesday, February 28th, 2023

Please join us as Ada Loo, chair of our Export Committee and Group Director and Associate General Counsel at Cadence Design Systems, hosts an export seminar on the impact of new regulations on the electronic systems design ecosystem. The breakfast meeting will be held Tuesday, March 28, from 8:30am until 11:30am at Cadence’s corporate headquarters in San Jose.

The session will feature the Cadence Government and Trade Group addressing general trade compliance concepts, how export control and sanction regulations affect the industry and current trends and emerging issues. Audience questions will be encouraged.

Speakers are Ada Loo and William Duffy, Cadence’s Corporate Counsel.

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A Look at the Practical Benefits of Formal Verification with Axiomise

Tuesday, February 21st, 2023

With DVCon U.S. next week, it’s appropriate to do a post on verification. I chose formal verification, a mathematical way of checking the behavior of a system to ensure that it works as intended.

To better understand formal and attempt to demystify it, I got in touch with ESD Alliance member Axiomise and its founder Dr. Ashish Darbari, CEO and Founder of Axiomise. Ashish is a well-known figure in verification circles for his formal expertise –– he received a Doctorate Formal Verification from the University of Oxford. Our conversation helped me appreciate and better understand the practical reasons why formal verification is becoming an important element in the verification toolbox.

I’m giving a talk at DVCon during Accellera’s lunch Monday on the CHIPS Act and its impact of the design and verification markets. Watch for a blog post from me about it.

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Silicon Assurance Outlines Growing Need for Hardware Security Systems

Wednesday, February 8th, 2023

 

Silicon Assurance, one of the ESD Alliance’s newest members, is a startup founded in 2021 to address security assurance and trust issues in silicon chips, as data breaches drive the need for better cybersecurity.

I recently spoke with Dr. Raj Gautam Dutta, co-founder and CEO of Silicon Assurance, to learn more about the challenge of building trust in silicon chips using the zero-trust security strategy model. A condensed version of our conversation is below.

Smith: What encouraged you to do an EDA startup?

Dutta: The plan to start the company was organic. A series of events unfolded in late 2018 and 2019 in the semiconductor industry including the discovery of the Spectre and Meltdown processor security flaws. That led us to believe it was the right time to open a company around the technologies we developed in our research labs at the University of Florida and the University of Central Florida.

In 2019, we saw increasing interest in our hardware security technologies from commercial semiconductor and EDA companies and had already licensed some of our technologies to these companies through the university. At that moment, we saw the need and opportunity to incorporate our technology into an EDA software package We had always envisioned taking our technologies from the lab to market and forming Silicon Assurance gave us the right platform to fulfill this objective.

Smith: What obstacles did you encounter?

Dutta: Since founding the company in 2020, we have faced many challenges. As all the founders are from academia with minimal industry experience, we have been navigating and carving out our path in this entrepreneurial world. Every step in developing the business has been a learning experience. We must also constantly remind ourselves of the difference between academic and business-oriented approaches/processes to EDA tool development. The company’s geographical location also created issues in terms of getting the attention of investors, potential customers, and employees.

The virtual communication landscape during COVID partially alleviated this challenge. We were able to conduct customer interviews and demo our software virtually. Hardware security technologies are new in the semiconductor space, and there have been many initiatives to raise awareness. However, the industry’s usage of such technologies has been slow presenting us with the challenge of driving a faster adoption rate.

Smith: Silicon Assurance focuses on chip security at the hardware level. Can you comment on the magnitude of the problem? What is the current state of chip hardware security?

Dutta: In 2019, Forrester Consulting surveyed companies with more than 500 employees for Dell Technologies. The survey showed that 63% of organizations experienced at least one data breach due to a hardware security vulnerability. The survey concluded that chip manufacturer validation and supply chain validation are critical to addressing hardware-level threats.

Subsequently, governments and the automotive industry want chips and electronic systems secure by design. In turn, the chip companies are demanding design tools that help them meet those requirements.

One way to quantify the magnitude of the problem is to look at the demand for tools for hardware security. As market data on hardware security tools are unavailable, we estimate that the total size of the hardware security tools market was over $130 million in 2021, and it is rapidly growing.

Smith: How do you define zero trust, and how is it different from “trust but verify?”

Dutta: Securing silicon chips and their supporting supply chains is crucial to prevent risks that threaten national security, global commerce and the continuity of our daily lives. Ensuring that the components and systems will behave as intended, free of defects and vulnerabilities, over their lifetime is essential to guarantee trust. Assurance strategies are a set of actions, evidence, and risk mitigation processes to ensure and demonstrate trust in a system to perform its mission.

One such strategy for delivering trust in chips is “Zero Trust.” In contrast to “trust but verify,” zero trust requires that no implicit trust be put in any one system component for example a specific device, chip or SoC. Trust should be built through continual fine-grained monitoring and authentication of the quantified risk before integrating the components (chips) into the larger system (SoC).

Smith: What trends do you expect to see in 2023?

Dutta: In 2023, we will continue to see the demand for hardware security solutions increasing. The market for devices that secure sensitive data, such as hardware security modules (HSM), is projected to grow from $1.1 billion in 2022 to $2.0 billion in 2027. The key factors contributing to the growth of HSM include the requirement for effective management of cryptographic keys and adhering to strict data security compliances. Today, there are more devices, data, security breaches, and regulations in the threat landscape. Consequently, we will see more industry sectors adopting such technologies rapidly.

Another trend we anticipate seeing in 2023 will be technologies that secure the semiconductor supply chain and chips. One of the objectives of the CHIPS Act of 2022 is to protect semiconductors from sabotage in the manufacturing process. There will be demand for technologies that protect chips at the design stage and track them throughout the manufacturing, assembly, testing, and packaging stages.

Learn more about Silicon Assurance at: https://siliconassurance.com/

About Raj Gautam Dutta

Dr. Raj Gautam Dutta is the co-founder and CEO of Silicon Assurance where his responsibilities include overlooking the technology development process, identifying business opportunities, and strategic positioning. He has been developing hardware security solutions for mor than eight years, and his research work has been published in prestigious journals and conferences. Dr. Dutta has over eight years of experience in technology transfer and technology analysis.

About the ESD Alliance

The ESD Alliance is a SEMI Technology Community representing members in the electronic system and semiconductor design ecosystem that addresses technical, marketing, economic and legislative issues affecting the entire industry. We act as the central voice to communicate and promote the value of the semiconductor design ecosystem as a vital component of the global electronics industry.

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