While 2016’s coming to an end, it’s not quite over yet and the month of December will be busy for the ESD Alliance.

Our industry has one brand new event called REUSE 2016 that will take place Thursday, December 1. The ESD Alliance will be there, along with close to 40 other exhibitors.

REUSE 2016 is the first of an annual conference and trade show to bring together the semiconductor IP supply chain and its customers for a full day of everything to do with semiconductor IP. It will be held from 11 a.m. until 8 p.m. at the Computer History Museum in Mountain View, Calif. Admission is free.

I’m moderating a conversation during REUSE with Lucio Lanza, managing director of Lanza techVentures, and Dan Rubin, general partner of Alloy Ventures. We’ll talk about the semiconductor IP market and IoT during the discussion titled, “IoT: Poised to offer huge growth opportunities for the global IP Business.”

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I had the pleasure of attending DVCon Europe in Munich, Germany, in mid-October to give the keynote address at the gala dinner. This was my first visit to the conference and I was impressed. As Oliver Bell of Intel and DVCon’s general chair wrote in his welcome greeting in the program, DVCon Europe is a practical, industry application-oriented conference, focusing on design and verification of electronic systems and integrated circuits. I found that to be absolutely true and then some. According to OneSpin’s Vice President of Marketing Dave Kelf, this year’s promotions chair, the conference attendance increased 20%. Kudos to the Steering Committee.
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October continues to be a busy month. I’m just back from a whirlwind trip to Munich, Germany, for DVCon Europe where I was the keynote speaker at the Wednesday night dinner. Stay tuned for a full report in my next blog post.

Meanwhile, if you’re going to ARM TechCon this week, please stop by the ESD Alliance Booth (#523) where you can learn about our programs and new initiatives and pick up a copy of our quarterly newsletter. The Expo Hall will be open Wednesday and Thursday from 10:30 a.m. until 6:30 p.m. at the Santa Clara Convention Center, Santa Clara, Calif.

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The ESD Alliance’s Emerging Companies Committee has a great topic, excellent moderator and an impressive group of panelists for the second in our ongoing series of panels on legal issues affecting small and emerging technology companies.

“Legal Steps to Maximize your Exit Value” will be held Tuesday, November 1, from 6 p.m. until 9 p.m. at Cadence’s corporate headquarters in San Jose, Calif. Attendees will learn about key valuation issues and techniques, along with more nuanced positioning strategies to build and lock-in enterprise value on exit transactions.
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Many thanks to Peggy Aycinena whose blog post is found above mine for her great profile of this year’s Phil Kaufman Award recipient, Andrzej Strojwas (pronounced Andrey Stroyvas), Keithley professor of Electrical and Computer Engineering at Carnegie Mellon University. If you haven’t read it as yet, I highly recommend it.

Andrzej is being recognized with the award, presented annually by the ESD Alliance and the IEEE Council on Electronic Design Automation (CEDA), for his pioneering research in the area of design for manufacturing (DFM) in the semiconductor industry. The relationship between design and manufacturing has never been more important and Andrzej deserves praise for recognizing early on that DFM needed to be a key element of chip design automation. His work was instrumental in bringing design and manufacturing together in a way that has benefited the semiconductor design and manufacturing communities as well as the broader electronics products markets.

The Phil Kaufman Award Ceremony and Dinner to honor him will be held January 26 at the Fourth Street Summit Center in San Jose, Calif., where we held last year’s dinner paying tribute to Mentor Graphics’ Wally Rhines. Wally was honored for growing the EDA and IC design industries through his efforts as a leading voice of EDA and for pioneering the evolution of IC design to SoC design.

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While many things keep me awake at night, concerns about IP tracking and security must keep many chip project managers from getting a restful sleep. That’s what convinced Warren Savage, chair of the ESD Alliance’s Semiconductor IP Working Group and general manager of Silvaco’s IP Division, to organize a panel “Semiconductor IP Issues that Keep You Up at Night.” It will be held Wednesday, September 14, from 6 p.m. until 8:30 p.m. at Silvaco’s offices in Santa Clara, Calif. Light snacks and beverages will be served during the networking hour from 6 p.m. until 7 p.m.

Warren will start the evening with an overview of the IP landscape. A panel will follow with experts Eric Stein from PwC and Rob Ballow of KPMG, who will share their advice on best practices, offer ways to implement them and answer audience questions. Eric and Rob are leading authorities on IP compliance from two of the largest worldwide auditing firms.

According to Warren, the massive amount of IP reuse involved in building an SoC has created a “big data” problem that is poorly managed by industry standards or methodologies. Instead, IP companies face a situation where their IP may be used without the proper license, leading to millions of dollars of lost revenue. Semiconductor companies face different issues but equally troubling as their engineers may inadvertently expose them to potentially huge liabilities as a result of “accidentally” reusing a core without the proper license.  Warren, Eric and Rob will outline commonly used practices used today and discuss new technologies that may help both buyers and sellers rest easier.

This event is open to all ESD Alliance member companies free of charge. Non-ESD Alliance members are welcome to attend at a cost of $40, payable online or at the door. For more information, click here. To register, click register.

As an expert in IP design and reuse, Warren worked with the Alliance to form the Semiconductor IP Working Group, our newest initiative. The group is working on a common methodologies and best practices for fingerprinting, and an end-to-end solution for tracking and auditing soft and hard IP that benefits both IP developers and vendors as well as IP users.

As I mentioned in several earlier blog posts, please contact me if your company is considering joining the ESD Alliance. Member companies will be eligible to receive information from or participate in the SIP Working Group’s efforts. Additionally, employees of member companies can participate in the SIP Working Group or some of the other initiatives offered by the Alliance. I’m always available to answer any questions about the Alliance and why your company should join. Please contact me at bob@esd-alliance.org.

Join us September 14 and have a better night’s sleep! We look forward to seeing you. For more information about the ESD Alliance, visit: www.esd-alliance.org.

Anyone in our industry who doesn’t believe system scaling is an industry movement need look no further than the IoT market of high-volume and low-cost devices. While these devices have exacting densities, performance and power requirements, advanced process technologies are a bit too risky and costly for IoT developers. IoT also requires heterogeneous functions such as digital, analog, mixed-signal, sensors and MEMS, a challenging proposition to mix all of these capabilities on a single die/process.

And, system scaling –– or multi-die IC –– is a viable integration alternative to traditional transistor scaling of newer process technologies. It integrates complex systems at the functional/building block level, not the transistor level. It doesn’t replace the need for the SoC. Instead, the SoC remains a key functional component of the system or, in die-form, a key building block of a multi-die IC.  System scaling relies on different advanced packaging technologies used to integrate and package multiple heterogeneous die.
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If you are planning to attend SEMICON West, please put the ESD Alliance booth on your Must See list so you can learn more about us. We will be in booth N1 in the North Hall at the Moscone Center in San Francisco. Exhibit hours are Tuesday, July 12, and Wednesday, July 13, from 10 a.m. until 5 p.m., and Thursday, July 14, from 10 a.m. until 4 p.m.

During SEMICON West, I will be a panelist on “The Path to Semiconductor and MEMS/Sensors Common Best Practices for Growth” discussion Wednesday from 2 p.m. until 3 p.m. It’s part of a workshop organized by SEMI and the MEMS & Sensors Industry Group titled, “From Collision to Convergence: Co-Creating Solutions in the Semiconductor and MEMS/Sensors Industries.” The workshop will run from 1 p.m. until 5 p.m. at the Marriott Marquis, just blocks from the Moscone Center.

To learn more, visit: http://www.semiconwest.org/

In case you missed it, here’s the link to the quarterly Market Statistics Service (MSS) report we published last week. It contains detailed revenue data for the EDA, Semiconductor IP, and design services industries. Overall, in first quarter 2016, we’re pleased to report industry revenues increased 4.5% compared to Q1, 2015. Total revenue for Q1 was $1962 million.
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The Design Automation Conference is over. The cowboy boots, 10-gallon hats and “Keep Austin Nerdy” T-shirts have been put in storage until DAC returns to Austin next year. For those of you from the electronic system design ecosystem who didn’t get to Austin this year, here’s a look at what you missed.

The parties –– from the opening reception, Jim Hogan’s Heart of Technology and IPextreme’s annual Stars of IP party hosted by Silvaco to the not-to-be missed Cadence’s Denali evening –– were lively, the Pavilion panel sessions and keynotes well attended and the giveaways were first rate.

Exhibitor feedback was positive, from my sampling, though you may have heard that attendance was down in Austin. While the attendee numbers haven’t been posted as yet, exhibitors didn’t seem phased by the perceived lower attendance. In fact, many noted that while the traffic at the show was smaller than in San Francisco, it provided higher quality attendees and more highly qualified prospects.

DAC was a great opportunity for the new Electronic System Design (ESD) Alliance to “strut our stuff” (minus the cowboy boots and Stetsons). Attendees and exhibits showed loads of interest in the new organization and stopped by our booth to learn more about our new, expanded direction and initiatives. Better yet, several companies committed to joining the Alliance based on our refreshed mission and momentum. Many others have asked us to follow up over the coming months.
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A reminder that the ESD Alliance –– a proud DAC co-sponsor –– will exhibit at DAC in Booth (#1920) Monday, June 6, through Wednesday, June 8, from 10 a.m. until 6 p.m. at the Austin Convention Center, Austin, Texas. Please stop by our booth to say hello and to learn more about our support of the Design Ecosystem. We’ll have plenty of informational handouts, including the latest edition of our newsletter, brochures on our new initiatives and membership packets.

Or, join us at the DAC Pavilion (Booth #1839) for, “Solving the Design Cost Puzzle: How intellectual property (IP) Fits,” featuring Jim Feldhan, president of Semico Research, Tuesday from 10:30 a.m. until 11 a.m. Jim will address trends and issues driving the rapidly growing market for third-party IP.

You’ll find many of us from the Alliance at the Gary Smith EDA kickoff Sunday from 5 p.m. until 5:30 p.m. in the convention center’s Ballroom D. Laurie Balch, a chief analyst for Gary Smith EDA, will open the annual reception with the annual update on the state of EDA, “Extending the Bounds of EDA.” The always well-attended DAC reception immediately follows.
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