Like so many others in the semiconductor industry, when someone mentioned the industry organization SEMI. I thought manufacturing and large events.

That was until I joined SEMI earlier this year as director of marketing for SEMI Americas. I quickly learned that SEMI is so much more than the industry perception that its sole purpose is to organize the 60 international semiconductor equipment and materials events it does each year.

For starters, it has 2,000 member companies and 1.3-million individual members in regions throughout the world, 5,000 volunteers and more than 170 programs. Members have access to SEMI in-house market data reports and R&D programs chock full of relevant information to help them make better, more informed business decisions. And, we’re celebrating our 1,000th standard, an important industry milestone we reached this summer.

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Now that SEMICON West is over, that summer vacation you dream of is closer than ever.

Before you head off to the beach, mountains or somewhere exotic, have a look at the photos of the keynote session and talks that were part of ES Design West, a first-time co-located event at SEMICON West.

ES Design West included a robust program of six Meet the Experts sessions with a total of 26 presentations and a techTalk session that had two speakers and a panel. Additionally, 22 exhibitors took the leap and helped pioneer the first ES Design West. Presentations will be available to ES Design West attendees.

A special nod to IBM who brought its IBM Q quantum computer to ES Design West showcasing quantum computing architecture built upon decades of semiconductor industry advances. Attendees saw demos of how the IBM Q Experience quantum cloud services platform and Qiskit, an open source quantum software framework, are used to program and experiment with real IBM Q systems.

Below are a set of photos from SEMICON West and ES Design West that captured the mood and enthusiasm that dominated the week in San Francisco. They were taken by Paul Cohen, senior manager of the ESD Alliance at SEMI.
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Note:  ES Design West, a co-located even at SEMICON West, continues today. Our final “Meet the Experts” session on Advanced Applications starts at 1:30 p.m. “Holistic Cost of Design” will be presented by Balachandran (Bala, for short) Rajendran, CTO, EDA at Dell EMC, the data storage giant, at 2:35 p.m. He and I recently talked about his views on efficient design flows.

On the surface, efficient chip design infrastructures doesn’t sound all that compelling as a topic. Until you talk with Bala. Bala is an engineer to the core, and on a campaign to efficiently reorganize engineering groups in a more holistic fashion backed by his 22+ years of experience in various roles in CAD, Infrastructure and IT. 

According to Bala, the cost of design and manufacturing is increasing drastically in the push to accelerate innovation. He goes on to say that the cost of design in newer technology nodes is twice the previous node, even though R&D efficiency is greater in the Semiconductor Industry.

The accelerated costs of design and manufacturing are due in large measure to added features in an SoC design that could impact size, power and performance, all of which means more design work and time. Of course, design, verification, software, IT, CAD and infrastructure groups continually optimize their environment in a move to make it more efficient and push it to the edge. They implement features and applications to improve the design and verification flow. All told, this well-intentioned practice is impacting design features and design quality. Modularity prevents progress.

One other factor that influences the overall environment is human resources, adds Bala. Often, a company that needs to get a design out faster will add headcount without recognizing that other factors should be considered as well. It’s less efficient and, remarkably, happens all the time.
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It’s a pleasure to welcome you to ES Design West and SEMICON West on behalf of the ESD Alliance, a SEMI Strategic Association Partner!

The ES Design West goal is to enable and accelerate conversations, information exchange and collaboration to address common issues, challenges and opportunities that move new electronic products from concept to consumer. We invite you to help us meet that goal as we proudly highlight commercial achievements of electronic system design, including IP, EDA, embedded software, design services and infrastructure including design in the cloud through an assortment of presentations and panel discussions.

As you walk the exhibit floor, meet colleagues and friends, and hear keynote speakers and other presenters, expect to talk about the growing links between electronic system and semiconductor design with the electronic product manufacturing and supply chain. It’s happening and it’s real.
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Moscone Center’s South Hall comes alive the week of July 8 with ES Design West, a new co-located event at SEMICON West. You can expect a memorable ES Design West with presentations, exhibits and so much more, all highlighting commercial achievements of electronic system design. 

Some BREAKING NEWS:  IBM will present its Q computer at ES Design West! You won’t want to miss the chance to see the Q, considered one of the foremost models for the future of computing to enable massive computations to solve some of the world’s previously unsolvable challenges. To find the Q demo area, look to the bottom right-hand corner of the South Hall floorplan.

IBM will present its Q computer at ES Design West.

If you haven’t already registered, you will want to do so today once you have a glance at our programs that run in the ES Design West SMART Design Pavilion Tuesday through Thursday, July 9-11. “Meet the Experts” topics range from More than Moore, Designing for Low Energy and Silicon Design in the Cloud to Machine Learning, AI, and EDA, Security and Advanced Applications. These presentations are intended for chip, system hardware and software designers and system integrators, and highlight commercial achievements of electronic system design.

As you’ll see, we have plenty to talk about. So much so that we took over TechTalk Stage South for one extra session, “TechTALK: Applied AI in Design-to-Manufacturing,” at 2 p.m. Tuesday.

Two “Meet the Experts” sessions will be held each of the three days in the Smart Design Pavilion. Kicking off Tuesday at 10:30 a.m. is “More than Moore,” an exploration of new ways to increase system functionality while reducing cost and size. Four presentations start with “Optimized Design to Manufacturing Flow for Process-Aware Chip to Package Modeling of Power Electronics” from Chan-Su Yun, Synopsys’ senior R&D manager. DARPA Program Manager Andreas Olofsson follows with “Status of the DARPA CHIPS Program.” “Next-Generation system-on-chip (SoC) Design: From Atoms to Systems” will be presented by Babak Taheri, Silvaco’s chief technology officer (CTO) and executive vice president of products. Concluding the session is Rupal Gandhi, Arm technical marketing manager, who will present “Best Internet of Things (IoT) practices for Arm Cortex CPU energy efficient implementation flows on Arm Artisan 22-nanometer platforms.”
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The ESD Alliance closes the month of May with news that Simon Segars, CEO of Arm, is chair of our recently elected 10-member Governing Council. 

The council unanimously nominated him to the position, and we’re pleased that he is our new chair.   We have plenty to accomplish moving forward with an exciting new set of programs and initiatives, especially as ES Design West kicks off in July. His knowledge, expertise, leadership and sound advice is welcome and valued.

Simon leads our Governing Council, a mix of long-time members and three newcomers, who will serve a two-year term. New Governing Council members are Dr. Raik Brinkmann, president and CEO of OneSpin Solutions, Dr. Prakash Narain, president and CEO of Real Intent and David Dutton, CEO of Silvaco.

Returning Governing Council members are:

• Aart de Geus, chairman and co-CEO of Synopsys, Inc.
• Dean Drako, president and CEO at IC Manage
• John Kibarian, president and CEO of PDF Solutions, Inc.
• Walden C. Rhines, CEO Emeritus of Mentor, a Siemens Business
• Lip-Bu Tan, CEO of Cadence Design Systems
• Bob Smith, Executive Director of ESD Alliance

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Last week was particularly eventful for the ESD Alliance. We finalized plans for the CEO Outlook, watched ES Design West momentum build and announced HOT Party news. This follows the evening we hosted two weeks ago with Jim Hogan and Cadence’s Paul Cunningham, effectively covered by Semiwiki’s Bernard Murphy and a Breakfast Bytes post from Paul McLellan, also of Cadence. 

We confirmed all of our panelists for the 2019 CEO Outlook Thursday, May 23, at SEMI in Milpitas, Calif. Moderator, Ed Sperling, editor in chief of Semiconductor Engineering, will lead a discussion with panelists John Chong, vice president of product and business development for Kionix, Jack Harding, president and CEO of eSilicon, John Kibarian, PDF Solutions’ president and CEO, and Wally Rhines, CEO emeritus of Mentor, a Siemens Business.

Ed Sperling

Clockwise from Left: John Chong, Jack Harding, Wally Rhines, John Kibarian.

Yes, we are mixing it up a bit to recognize our move into SEMI where our collective focus is on the broader electronic product design and manufacturing chain.

To do that, we invited two panelists from the ESD Alliance community and two with experience and expertise in other segments of the chain –– Kionix and eSilicon.

Kionix, a division of Rohm, is the third largest supplier of MEMs devices to the electronics industry. John is also the chair of the MEMS and Sensors Industry Group (MSIG), a SEMI Strategic Association Partner.

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While we finish the last few details, set aside the evening of Thursday, May 23, so you won’t miss our CEO Outlook. Moderated by Ed Sperling, Semiconductor Engineering’s editor in chief, it begins at 6pm with dinner, refreshments and networking, followed by a panel of industry CEOs from 7-8:30pm. We always save room for audience questions.

If your company is not a member of the ESD Alliance, now a SEMI Strategic Association Partner, consider joining to become part of an expanding system design ecosystem. The ESD Alliance website is full of information about our technical committees and other initiatives, as well as a listing of the events we sponsor. I’m available to answer questions about why joining the ESD Alliance is important for staying current. I can explain ROI or other justifications for joining and can be reached at bsmith@semi.org

More Details about ES Design West

Also moving along briskly is our planning for ES Design West, as is a growing exhibitor list. The event, co-located with SEMICON West 2019 July 9-11 at San Francisco’s Moscone Center South Hall, will showcase innovation, contributions and commercial successes made possible by the system and semiconductor design ecosystem.

Is this tantalizing enough for you? No? Then:

• Imagine the chance to participate in something brand new.
• Visualize a unique, new brand identity and place for design ecosystem members, including a dedicated theater for presentations on commercial achievements of our community and forward-looking, system-centric design approaches.
• Realize that design and manufacturing are drawing closer together and that a co-location at SEMICON West will bring together the entire electronic product chain into one super-charged event.
• Remember San Francisco draws attendees from Silicon Valley and the greater Bay Area, still the heart of technology, as well as other locales.

All this and more will help attendees and exhibitors better understand the links between design and manufacturing. Program details, registration information and an exhibitor prospectus can be found at the ES Design West website. Follow ES Design West on Twitter: #ESDesignWest

We look forward to seeing you at one or both of these exciting events.

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Jim Hogan and the ESD Alliance, a SEMI Strategic Association Partner, changed up our typical “Crossing the Chasm” event. Instead, Jim, managing partner of Vista Ventures, LLC., will interview Paul Cunningham, corporate vice president and general manager of the system verification group at Cadence Design Systems, in an informal “Fireside Chat.”

Please join us Wednesday, April 10, for a sweeping conversation with plenty of time for questions from attendees. Jim and Paul have a lot to talk about, including a bit about Paul’s “Crossing the Chasm” experience when he founded Azuro and served as its CEO through its subsequent acquisition by Cadence in 2011. Earlier in his career, Paul worked in artificial intelligence before it was an industry trend. Today, he’s managing Cadence’s system functional verification activities.

Attendees can expect to learn about Paul’s move 18 months ago from managing physical design tools development into verification and the challenges ahead. Other topical subjects under discussion include open source architectures and the necessary development platforms.

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The long wait is over –– the ES Design West website is live and registration is open! We’re hosting the co-located event during SEMICON West at San Francisco’s Moscone Center (South Hall) July 9-11 to promote and highlight system design innovation.

Take a stroll through our colorful website chock-full of details about this brand new expo. You’ll find we have our own unique brand, identity and area for design ecosystem members including our own “Meet The Experts” Theater. Presentations and panel discussions will showcase commercial successes of the design ecosystem, including IP, EDA, embedded software, design services, design infrastructure and design in the cloud.

Any visitor to the ES Design West website will learn quickly it is about to become the must attend expo promoting and highlighting system design innovation. We’re focused on showcasing the commercial aspects and successes of the various segments of the electronic system and semiconductor design ecosystem. Co-locating at SEMICON West provides a venue that naturally brings the entire electronic product chain together in one much larger event.

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