Accellera Systems Initiative – or Accellera – is a standards organization well-regarded by the electronic design automation (EDA) ecosystem that’s also served by the ESD Alliance, a SEMI Technology Community. Lu Dai, Senior Director of Technical Standards at Qualcomm, has chaired the Accellera Board of Directors since 2017. I recently spoke with Dai about the importance and efficacy of semiconductor industry standards.

Smith: Standards are a way of life in EDA and across the semiconductor industry. Why are they so important?

Dai: Accellera Standards represent a collaboration of the best ideas in the industry to support product development. They help build an ecosystem and foster innovation through sharing of ideas and practices instead of re-invention.

Smith: Accellera was formed when Open Verilog International and VHDL International, two important verification organizations, merged in 2000. What is Accellera’s greatest standards success to date?

Dai: Our SystemVerilog is our biggest success because it united Verilog and VHDL, the standards that started Accellera, though we’ve produced a number of compelling standards including Verilog, VHDL, System Verilog, SystemC, UPF and UVM, our most downloaded standard. It can be downloaded for free as part of our IEEE GET Program. Additionally, a video on UPF is the most watched of our videos worldwide. Among our forum discussions, SystemC is the most active of our standards.

Smith: How have standards helped improve the chip design verification flow?

Dai: Our Verilog/VHDL, SystemC and SystemVerilog standards established verification as a stand-alone profession, and standards such as UVM allow verification to scale as design complexity increases. IP-XACT, SystemRDL and UPF standards enable SOC design. Our most recent standards, such as Portable Stimulus Standard 2.0 and SA-EDI 1.0, continue to push the boundaries of design and verification, helping to improve productivity.

Smith: What new standards are in the queue to be ratified and adopted?

Dai: Our Functional Safety Working Group has been focused on a standard data model for capturing and propagating the safety intent from the system down to the SoC / IP design and implementation including failure mode propagation, verification, validation, reliability and Safety Mechanisms. The safety intent standardization will support data exchange and traceability across different safety analysis and work products and will enable operability and traceability in different domains including digital, analog, package, PCB and software as well as across industry segments and supply chains.

Our Portable Stimulus Working Group will have some significant updates to its latest standard in the next few months. This includes deprecating C++ support, adding scenarios-level coverage, new core library additions of solve/runtime messaging and new randomization capabilities through new syntax or expanded expectation on existing syntax.

Smith: What standardization effort is next for Accellera?

Dai: Our standards are driven by interest and need from the design community and as a result, we have several analog/mixed-signal standards in the development pipeline such as SystemVerilog-AMS, SystemC-AMS, and UVM-AMS. We have also recently formed a new Clock Domain Crossing (CDC) Working Group to develop interoperable CDC modeling to facilitate IP-SOC handoff and system-level CDC verification.

We closely monitor market trends, technology developments and innovations, and government R&D policies that may influence our priorities and reveal new areas where standards may be of benefit. Areas we keep a close eye on include supply chain security, chiplet-based design and verification, the renewed focus on advanced packaging to accommodate design complexity and AI/ML-based design and verification. We also track federated simulation where distributed simulation over potentially divergent platforms and abstraction is needed to handle complex system-level Design Under Test.

Smith: How long have you been part of Accellera? What made you get involved with Accellera?

Dai: I joined the Accellera Board of Directors in 2015 and became chair in 2017. I have been involved in ASIC design and verification for almost 30 years, with a full-time focus on verification the last 20 years.

I led Qualcomm’s SoC verification organization and the development of many generations of Snapdragon SoC verification. I have always been fascinated by standards work, especially the early discussions for and against Verilog vs. VHDL and the many concerns about incompatibility and loosely defined constructs. I decided the best way to influence was to get involved in fixing the problem.

Smith: Standards efforts require tireless and dedicated volunteers. How can someone who believes in verification standards get involved?

Dai: Accellera welcomes new member companies that are interested in standards and want to contribute ideas through representatives. I encourage interested engineers to keep a notebook of their ideas or concerns and set aside time to work through the problem and come up with potential solutions. Hopefully they work for a company that believes in and supports the value of standards and are willing to contribute resources to the standardization effort. Our forums are open to the public, so that is also a good place to contribute ideas and ask questions if someone is interested but their company is not already a member.

About Lu Dai

Lu Dai is Senior Director of Technical Standards at Qualcomm, leading semiconductor standards and industry organizations. Lu was previously Senior Director of Engineering and led Qualcomm’s SOC design verification team and front-end methodologies and initiatives. Dai was the Design Verification Lead responsible for multiple generations of Premium Tier lead chips at Qualcomm, including the best-selling Snapdragon 800 that powers Mars Perseverance rover and Ingenuity helicopter. Dai holds a Master’s degree in Electrical Engineering from Cornell, and a Bachelor’s in Electrical Engineering and Computer Science from UC Berkeley.