EDACafe: Bridging the Frontier

Archive for March, 2023

Rescheduled! Export Seminar on Impact of New Regulations on the Semiconductor Design Ecosystem

Wednesday, March 29th, 2023

Originally scheduled to be held in March, “The Impact of New Regulations on the Semiconductor Design Ecosystem,” was postponed due to scheduling conflicts to Wednesday, April 26, from 8:30-11am at Cadence’s corporate headquarters in San Jose, Calif.

The seminar, presented by SEMI’s ESD Alliance Export Committee, will be hosted by Ada Loo, chair of the ESD Export Committee and Cadence’s Group Director and Associate General Counsel. Attendees will learn why and how governments implement trade controls and what “exports” are and how they take place in different business contexts. Explanations will help clarify common due diligence methods, such as customer screening, that U.S. companies use to incorporate regulatory compliance into their business processes. The seminar also will focus on recent regulatory updates that address current issues including U.S.-China trade relations and the anticipated effects of those regulations on the US semiconductor design ecosystem.
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License Server Certification Task Force Formed

Tuesday, March 21st, 2023

The design and manufacture of today’s semiconductor chips is a complex process, requiring advanced software tools throughout the design to manufacturing flow. These tools require a team of talented engineers to develop and maintain. As the industry advances to smaller geometries and heterogeneous integration, new challenges arise requiring more research and development of the software used throughout the design ecosystem. These efforts are funded through the sale and licensing of the software.

One of the ongoing efforts of the Electronic System Design Alliance (ESD Alliance), a SEMI Technology Community, is the License Management and Anti-Piracy Committee (LMA). Part of the committee’s purpose is to help reduce the incidence of unauthorized use (piracy) of this complex software. Unauthorized use negatively impacts both the tool vendors and customers. It deprives the software developers of revenue for their continuing efforts to develop new products that address the increasingly complex design ecosystem. Software piracy impacts the legitimate users of the software in two ways. First, the vendors may need to increase prices to be able to continue their R&D of new products and functionality. Second, it provides an unfair competitive advantage to those companies who are not paying for the software.
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An Epic Chiplet Evolution

Monday, March 13th, 2023

Note: I recently talked with Jean-Marie Brunet, Vice President and General Manager of the Siemens Hardware-Assisted Verification business unit, about the growing use of chiplets. He has a unique perspective that’s captured below in a blog post I wrote for 3D InCites.

Jean-Marie Brunet, Vice President and General Manager of the Siemens Hardware-Assisted Verification business unit finds himself and his group in a unique situation when it comes to the topic of chiplets. The group designs a chiplet for their own products and sells those products to verification engineers who are verifying chiplet designs.

I recently had a conversation with Jean-Marie to get his perspective on chiplets and why he believes they are leading an epic chiplet evolution.

Smith: A significant challenge to chiplet adoption is scaling. Is that the biggest challenge or are there more pressing challenges?

Brunet: It’s a big topic. First, let me explain why. I manage an organization that develop hardware verification technology to the market –– emulators and FPGA prototyping hardware.

In the case of the emulator, we create all parts of the emulator. We build a very large device with a complex hardware architecture that must run a large amount of software. By developing our own hardware, we understand scaling challenges.

In terms of scaling, there is a lot of talk about how Moore’s Law is dead. No, Moore’s Law is doing just fine. Today semiconductor companies are designing for two or three nanometer process technology that uses a different type of transistor so it’s very expensive to go to an advanced node.
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