It’s with great pleasure that I’m able to announce Maheen Hamid, Chief Operating Officer and Chief Financial Officer of Breker Verification Systems, is now a member of the Electronic System Design Alliance Governing Council.

Maheen Hamid

Maheen, a seasoned, accomplished executive, assumes the seat formerly held by Babak Taheri who was CEO/CTO of Silvaco. She brings more than 15 years of financial experience in deal structuring and operations management in diverse industries including wireless telecommunications, clean energy, health, and infrastructure projects in emerging markets. Prior to Breker, Maheen served in various roles in investment banking and management consulting and is an occasional contributor to different business journals and forums covering a broad range of topics related to management. She holds a BBA from North South University in Bangladesh and an MBA from the University of Texas at Austin.

“I am delighted to be joining the governing council of this important organization at a key moment in its history,” Maheen is quoted as saying in the news release announcing her appointment. “As Breker has grown to become an established EDA company working with semiconductor companies in the area of test suite synthesis, we have gained a wealth of experience and I hope to bring this perspective to the council.”

Maheen will serve a two-year term that runs through 2023, along with:

• Aart de Geus, chairman and co-CEO of Synopsys, Inc.
• Dean Drako, president and CEO at IC Manage
• Aki Fujimura, D2S’ CEO
• John Kibarian, president and CEO of PDF Solutions, Inc.
• Prakash Narain, president and CEO from Real Intent
• Joe Sawicki, executive vice president of Siemens EDA
• Simon Segars, CEO of Arm, who serves as the Governing Council Chair
• Bob Smith, executive director of the ESD Alliance

Many readers know Breker Verification Systems as a chip design verification company founded in 2003 by Maheen and her husband Adnan Hamid. Specially, it provides Portable Stimulus solutions, a standard means to specify verification intent and behaviors reusable across target platforms.

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We did it again! The electronic system design (ESD) ecosystem reported a revenue increase of 14.6% year-over-year from $2,783.9 million to $3,191.4 million in Q2 2021. Our latest Electronic Design Market Data (EDMD) report comparing the most recent four quarters to the prior four also found that the four-quarter moving average rose 15.5%, the highest annual growth since 2011.

According to Wally Rhines, executive sponsor of the SEMI EDMD report, double-digit growth was reported in Computer Aided Engineering (CAE), Printed Circuit Board and Multi-Chip Module (PCB and MCM), Semiconductor IP (SIP) and Services. In addition, all geographic regions reported growth on a rolling four-quarter basis, with the Americas; Asia Pacific (APAC); and Europe, Middle East, and Africa (EMEA) showing a substantial year-over-year increase.

It also tracks total employment at participating companies. In the latest report, companies employed 49,964 people globally in Q2 2021, a 7.3% increase over the Q2 2020 headcount of 46,579 and up 1.9% compared to Q1 2021.

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I’m pleased to welcome Aselta Nanographics and Metis Microsystems to the ESD Alliance community. Both have countless reasons for joining. For example, Yorick Trouiller, Aselta Nanographics’ CEO, noted: “Joining the ESD Alliance is a great opportunity to stay connected with the EDA community and take an active part in the discussions driving the future of semiconductor manufacturing.”

According to Azeez Bhavnagarwala, founder of Metis Microsystems, “As a startup dedicated to enabling energy efficiency in semiconductor products, we are excited about the opportunities the ESD Alliance and SEMI offer to connect with the network of industry members. Both the ESD Alliance and SEMI have initiatives and resources offered by their domain-specific Smart Initiatives, Technology Communities and Committees that can help us understand and engage with industry members as a startup on topics of common interest.”

Our New Members

Aselta Nanographics of Grenoble, France, provides advanced software solutions for wafer and mask patterning based on e-beam technology. It develops software tools to improve the quality process of chip production and operates in the IC manufacturing world providing advanced software solutions for wafer and mask patterning based on e-beam technology as well as solutions for contour-based metrology. Aselta Nanographics is a spin-off of CEA-Leti and maintains strong links with cutting-edge fundamental research and applies it to deliver advanced industrial solutions to customers in the U.S., Europe and Asia.

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