A reminder to join Accellera and the ESD Alliance tomorrow as we co-host panel of experts who designed and verified chips during a pandemic. Register today for next week’s discussion (Wednesday, June 9, from 9-10am PDT).

Moderator: Tom Fitzpatrick, Strategic Verification Architect, Siemens EDA

Panelists:

Martin Barnasconi, Technical Director System Design & Verification Methodologies, NXP

Lu Dai, Senior Director of Engineering, Qualcomm

Dr. Ashish Darbari, CEO, Axiomise

Mark Glasser, Member of the Technical Staff, Cerebras

Patrick Lynch, Senior Engineering Manager, Xilinx

Complimentary registration: https://form.jotform.com/211165237551955