Bridging the Frontier 
Bob Smith, Executive Director
Bob Smith is Executive Director of the ESD Alliance responsible for its management and operations. Previously, Bob was senior vice president of Marketing and Business Development at Uniquify, responsible for brand development, positioning, strategy and business development activities. Bob began his … More » ES Design West Sessions Highlight Commercial Achievements of Electronic System DesignJune 20th, 2019 by Bob Smith, Executive Director
Moscone Center’s South Hall comes alive the week of July 8 with ES Design West, a new co-located event at SEMICON West. You can expect a memorable ES Design West with presentations, exhibits and so much more, all highlighting commercial achievements of electronic system design. Some BREAKING NEWS: IBM will present its Q computer at ES Design West! You won’t want to miss the chance to see the Q, considered one of the foremost models for the future of computing to enable massive computations to solve some of the world’s previously unsolvable challenges. To find the Q demo area, look to the bottom right-hand corner of the South Hall floorplan.  IBM will present its Q computer at ES Design West. If you haven’t already registered, you will want to do so today once you have a glance at our programs that run in the ES Design West SMART Design Pavilion Tuesday through Thursday, July 9-11. “Meet the Experts” topics range from More than Moore, Designing for Low Energy and Silicon Design in the Cloud to Machine Learning, AI, and EDA, Security and Advanced Applications. These presentations are intended for chip, system hardware and software designers and system integrators, and highlight commercial achievements of electronic system design. As you’ll see, we have plenty to talk about. So much so that we took over TechTalk Stage South for one extra session, “TechTALK: Applied AI in Design-to-Manufacturing,” at 2 p.m. Tuesday. Two “Meet the Experts” sessions will be held each of the three days in the Smart Design Pavilion. Kicking off Tuesday at 10:30 a.m. is “More than Moore,” an exploration of new ways to increase system functionality while reducing cost and size. Four presentations start with “Optimized Design to Manufacturing Flow for Process-Aware Chip to Package Modeling of Power Electronics” from Chan-Su Yun, Synopsys’ senior R&D manager. DARPA Program Manager Andreas Olofsson follows with “Status of the DARPA CHIPS Program.” “Next-Generation system-on-chip (SoC) Design: From Atoms to Systems” will be presented by Babak Taheri, Silvaco’s chief technology officer (CTO) and executive vice president of products. Concluding the session is Rupal Gandhi, Arm technical marketing manager, who will present “Best Internet of Things (IoT) practices for Arm Cortex CPU energy efficient implementation flows on Arm Artisan 22-nanometer platforms.” “Designing for Low Energy” continues the “Meet the Experts” program Tuesday at 1:30 p.m. and examines how designing for low energy is evolving with new design techniques, intellectual property (IP) and software solutions. To commence the session, Helena Handschuh, Rambus security technologies fellow, addresses “Low power, low energy and high security: dream or reality?” “DVFS –– A New Dynamic for Low-Energy Embedded Systems,” will be outlined by David Baker, chief architect at Eta Compute. “Edge Computing: Changing the balance of Power” is the next presentation from Nihaar Mahatme, NXP technology strategy lead, Microcontrollers Business Line. Lauri Koskinen, CTO and co-founder of Minima Processor, offers a look at “Dynamic Margining Lowers Voltage and Energy in Real Time.” “Energy Efficient ASIC Methodology” by Godwin Maben, Synopsys scientist, wraps up the session. “TechTALK: Applied AI in Design-to-Manufacturing” Tuesday at 2 p.m. at TechTalk Stage South begins with “Everything Needs a Digital Twin in the Deep Learning Era” by Aki Fujimura, D2S chairman and chief executive officer (CEO). Semico Research Principal Analyst Richard Wawrzyniak proposes “The Emergence of AI and its Impact on the Semiconductor Industry.” “The Cognitive Edge” will be discussed by Jan Rabey, professor, University of California at Berkeley and CTO System-Technology co-optimization, IMEC, Belgium. A panel session follows titled, “Are We Experiencing a Renaissance in Chip Design and EDA?,” moderated by Jim Hogan, managing partner of Vista Ventures, featuring select industry experts. The Wednesday morning session at 10:30 a.m., “Silicon Design in the Cloud,” charts the current and future of cloud-based design as considered by silicon design tool users, developers, and cloud solution providers. President and CEO of ICManage Dean Drako leads off with “Five Fundamentals to a Hybrid Cloud.” David Pellerin, head of global business development at Amazon Web Services, follows with “Semiconductor Design and Verification at Cloud Scale.” “Accelerating Silicon Design via Cloud and AI/ML” is next up and will be presented by Mujtaba Hamid, head of product management, silicon, electronics and gaming at Microsoft. The final presenter is “Lessons Learned from Assisting the Early Adopters of Cloud-Based IC Design” from Craig Johnson, vice president, Cadence cloud team of Cadence. The Wednesday afternoon session beginning at 1:30 p.m., “Machine Learning, AI, and electronic design automation (EDA),” will survey the impact of voice and image recognition, machine learning and AI applications on EDA tools. “Transforming Design with AI –– Opportunities and Challenges” from Synopsys Fellow Manish Pandey opens the session, followed by “Far Field Voice Recognition using Machine Learning” given by Hamid Nawab, chief scientist and technology advisor of Yobe. Pete Warden, Google staff research engineer, considers “What Machine Learning Needs from Silicon.” Next is “Solving Control Problems Using Small Neural Networks” presented by Oliver King-Smith, CEO of Smartr-ai. “Implementation of a Voice Trigger using Low-Power Processors,” from Laurent Le Faucheur, Arm principal engineer, Digital Signal Processing and Machine Learning, concludes the session. Security is the topic for Thursday morning’s “Meet the Experts” session that starts at 10:30 a.m. Attendees can expect to hear speakers discuss security concerns and risks in today’s designs, beginning with “IoT Security –– One Feature is Not Enough!” by Mike Eftimakis, Arm’s senior IoT product manager. Ed Sperling, editor in chief of Semiconductor Engineering, leads a discussion on “Raising the Threat Level on Hardware.” Sylvian Guilley, CTO of Secure-IC, will present “Use cases for embedded secure elements.” The final presentation “Zero-Touch Security Provisioning for IoT” will be given by Richard Kerslake, IoT program director, Internet of Things Group of Intel. The final session in the “Meet the Experts” program will survey “Advanced Applications” or tools and methodologies to develop complex chips, along with advanced verification methodologies to assure correctness. “Five Best Practices for Static Verification Sign Off” will be given by President and CEO of Real Intent Prakash Narain. Graham Bell, Silvaco’s senior director of marketing, steps in to present “High-Sigma Statistical Analysis: What is the Need and How to Deploy?” “Holistic Cost of Design” is the title of the talk from Balachandran Rajendran, CTO, EDA of Dell EMC. Tim Heighway, Arm principal application engineer, offers “Addressing Complexity in SoC Design.” The final presenter is Bipul Talukdar, SmartDV’s director of Applications Engineering North America, who will describe “Design Successes with Verification IP.” ES Design West badge holders can attend six SEMICON West keynote talks at the Blue Shield of California Theater over the three-day conference. Keynote presenters include Gary Dickerson, president and CEO of Applied Materials, AMD President and CEO Lisa Su, Aart de Geus, Synopsys chairman and co-CEO, and Bob Pearson, author and senior Advisor at W2O Group. Other keynote speakers are Dean Kamen, founder of DEKA Research & Development Corporation and founder of FIRST® (For Inspiration and Recognition of Science and Technology), and Jeffrey Welser, vice president and lab director of IBM Research-Almaden. Exhibit hours for ES Design West, hosted by Electronic System Design (ESD) Alliance, a SEMI Strategic Association Partner, are Tuesday and Wednesday 10 a.m. until 5 p.m. Thursday hours are 10 a.m. though 4 p.m. A more detailed program, exhibitor floor plan, networking and registration information can be found at the ES Design West website. Follow ES Design West on Twitter: #ESDesignWest The HOT Party And, don’t forget the Heart of Technology (HOT) fundraising party at ES Design West and SEMICON West Tuesday, July 9. Sponsored by Jim Hogan and co-sponsors, it will be held at the John Colins Lounge in San Francisco from 5:30 p.m. until 10 p.m. ES Design West and SEMICON West badge holders will be admitted with a suggested minimum tax-deductible $20 donation. Other guests can attend for a tax-deductible donation of $50.
This year’s beneficiary is the SEMI Foundation supporting Science, Technology, Engineering and Mathematics (STEM) education and career awareness in high technology. All proceeds from the event will be contributed to the SEMI Foundation. Event co-sponsors are ESD Alliance, eSilicon, Burr & Forman, LLP, Sage Design Automation, Harvest Management Partners, LLC, Breker Verification Systems, Pulsic, OneSpin Solutions, Methodics, SEMI, Silvaco, Big Kahuna Productions and Mod Marketing. I’ll cover the exhibit floor in next week’s blog post. Until then, I encourage you to register for ES Design West so you don’t miss hearing talks about the future and helping us celebrate the electronic system design ecosystem’s commercial achievements. To register, go to: https://bit.ly/2ut4zZx Questions or comments? Contact me at bsmith@semi.org Follow the ESD Alliance ESD Alliance Bridging the Frontier blog Twitter: @ESDAlliance |
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