First Visit to DVCon Europe Leaves Positive Impression

I had the pleasure of attending DVCon Europe in Munich, Germany, in mid-October to give the keynote address at the gala dinner. This was my first visit to the conference and I was impressed. As Oliver Bell of Intel and DVCon’s general chair wrote in his welcome greeting in the program, DVCon Europe is a practical, industry application-oriented conference, focusing on design and verification of electronic systems and integrated circuits. I found that to be absolutely true and then some. According to OneSpin’s Vice President of Marketing Dave Kelf, this year’s promotions chair, the conference attendance increased 20%. Kudos to the Steering Committee.

DVCon Europe is in its third year and, from all I saw, it’s a lively conference full of interesting sessions that ranged from tutorials and panels to keynotes and technical presentations. Twenty-four exhibitors, including ESD Alliance members Cadence, Mentor Graphics, OneSpin Solutions, Sigasi and Synopsys, demonstrating design and verification tools and services rounded out the full two-day event. Of course, conference organizers ensured there was plenty of time for networking and information exchange.

The dinner was held at the mid-point of conference –– Wednesday evening –– and everyone attending the conference appeared to be there. My talk titled, “Moore’s Law and the Transition from Chip-Centric Design to System-Level Design,” was geared to this European design and verification community. However, the message seems to have international appeal

My talk was geared to the European design and verification community. It covered the shift from Moore’s Law and chip-centric design to system-level design.

It’s apparent that the semiconductor design ecosystem is evolving from a chip-centric focus to a system-centric worldview. While SoCs and other complex semiconductor devices continue to be critical building blocks, the design emphasis is shifting to system design. Moore’s Law remains a key driver, though there are roadblocks and the industry is beginning a transition from integration at the transistor level to integration at the functional or block level.

It’s a great opportunity for many of us in the semiconductor industry and especially attendees at DVCon Europe and similar conferences. And, in fact, it’s why we rebranded the 27-year old EDA Consortium to the ESD Alliance earlier this year to meet the requirements of this evolution. If you haven’t looked lately, please check out the ESD Alliance website to see a refreshed mission acknowledging the breadth of activity we’re undertaken to support the entire system design ecosystem.

I thank the DVCon Steering Committee, especially Oliver Bell and Dave Kelf for inviting me to deliver the keynote and giving me the chance to observe a healthy and vibrant European conference. If you’re planning ahead, the original DVCon will be held in February 27-March 2, 2017 in San Jose, Calif. And, the inaugural DVCon China is slated for April 19, 2017 in Shanghai, China.

The ESD Alliance is well positioned to become the central voice to communicate and promote the value of the system design ecosystem as a vital component of the global electronics industry. As this edition of the ESD Alliance newsletter highlights, our membership is growing, our initiatives expanding and we’re offering more events and opportunities. If your company is not a member as yet, please consider joining now. To learn more about the ESD Alliance and how your company can become a member, contact me at bob@esd-alliance.org or visit www.esd-alliance.org

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