Posts Tagged ‘UPF’
Tuesday, April 2nd, 2013
Cary Chin, Director of Technical Marketing at Synopsys, has an intriguing take on how to approach verification now that the mandate for design project managers is to meet the low power requirement of the target end-product. Chin says that if we look at verification in terms of fine and broad “granularity,” users will meet their verification goals with a lot less angst and anguish. However, at first glance, I had no idea what Chin was talking about…which is why we asked him to join us and talk about this idea.
Ed: Cary, you’ve been recently talking about granularity in verification, especially in terms of low power. What does this all mean?
Cary: When I think of granularity in low power design, I’m thinking about the size of the “chunks” that we manipulate to improve the energy efficiency (or “low power performance”) of a design. For example, in most of today’s low power methodologies, large functional blocks are the boundaries we work within – we can shut down these blocks or manipulate the voltage to save energy when peak performance isn’t required. This boundary level isn’t just a matter of convenience; our tools and methodologies for both implementation and verification can only deal with certain levels of complexity, so we are confined in many dimensions in how we can pursue finer granularity.
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Tags: EDA, Electronic Design Automation, granularity, hardware, low power, low-power verification, Moore's Law, power, RTL, semiconductors, software, Synopsys, UPF, verification
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Wednesday, October 10th, 2012
 Narayana Koduri’s article on Power Awareness in RTL Design Analysis was the second of two Atrenta articles that EE Times editor Brian Bailey named as the ten most-read contributed articles published in EDA Designline. Along with number one article Understanding Clock Domain Issues by Saurabh Verma and Ashima Dabare, Atrenta appears to be the only company with two articles in this top ten list.
So even though his article appeared in July 2012, we asked Narayana to give us an update on what he sees as the power awareness challenges. Here’s what he had to say.
Ed: Narayana, your article sure addressed a hot topic in SoC design. And judging by the readers you got, the design community liked what you had to say. What can you add to your July 2012 article?
Narayana: Thanks Ed. From what I can see, due to aggressive low power requirements, power domains are being implemented in a growing number of SoC designs to reduce both leakage and dynamic power.
Ed: How so?
Narayana: UPF or CPF can be used to define the power intent to capture information such as power domains, level shifter requirements, isolation cells, retention cells, power switch cells, etc. These specifications will help implementation tools and verification tools to deal with the power intent properly.
Ed: So how best to deal with power intent?
Narayana: RTL tools that verify aspects of the SoC such as clock domain crossings, testability, timing and routing congestion need to be aware of the power intent. If not, the verification is not complete and this may lead to design failures or a costly re-spin of the design. This need for power-aware verification is driving new requirements in the EDA tool flow.
NOTE: For an update on Understanding Clock Domain Issues see our blog of October 3.
Note: Lee PR does work for Atrenta
Tags: Atrenta, Brian Bailey, CDC, CPF, EDA, EDA DesignLine, EE Times, low power, Power awareness, power domains, register transfer level, RTL, semiconductors, SoC, UPF, verification
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Thursday, January 12th, 2012
This year, we’ll see an old standards battle get resolved. Now that all the players are participating in the IEEE Standard 1801 project (IEEE Standard for Design and Verification of Low Power Integrated Circuits), we can finally put the UPF-CPF debate to rest. Let’s hope that peace will reign and the temptation to fight one more time about a single low power standard will be overcome.
Social media will become less of a curiosity or a perceived waste of time for engineers. We’ll see more EDA customers helping answer each other’s questions and sharing more information (nothing proprietary, of course). LinkedIn discussions will have more depth, not simply people posting “read my blog”.
Facebook will remain more of a social vehicle, and for many engineers of our generation, a misunderstood channel. YouTube videos that provide good content – “how-to” and learning opportunities – will become popular. Twitter will remain a mystery for most, while a minority will find it of much value (include me in the minority). Marketers who spam social media channels with marketing-speak will be shunned. And, we’ll have some great guests on Conversation Central radio.
Karen Bartleson
Sr. Director, Community Marketing
Synopsys, Inc.
@karenbartleson
www.synopsys.com/blogs/thestandardsgame
President-Elect, IEEE Standards Association
Tags: @karenbartleson, 2012, Conversation Central radio, CPF, DAC, Design Automation Conference, EDA, EDA & IP, Electronic Design Automation, Facebook, IEEE, IEEE Standard 1801, IEEE Standards Association, IP, Lee PR, LinkedIn, Low Power ICs, Semiconductor IP, semiconductors, social media, Standards, Synopsys, Twitter, UPF, www.leepr.com, YouTube
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