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Posts Tagged ‘power’

Granularity and complexity in low power verification

Tuesday, April 2nd, 2013

 

 

Cary Chin, Director of Technical Marketing at Synopsys, has an intriguing take on how to approach verification now that the mandate for design project managers is to meet the low power requirement of the target end-product.   Chin says that if we look at verification in terms of fine and broad “granularity,” users will meet their verification goals with a lot less angst and anguish.    However, at first glance,  I had no idea what Chin was talking about…which is why we asked him to join us and talk about this idea.

 

Ed: Cary,  you’ve been recently talking about granularity in verification, especially in terms of low power.  What does this all mean?  

Cary:  When I think of granularity in low power design, I’m thinking about the size of the “chunks” that we manipulate to improve the energy efficiency (or “low power performance”) of a design.  For example, in most of today’s low power methodologies, large functional blocks are the boundaries we work within – we can shut down these blocks or manipulate the voltage to save energy when peak performance isn’t required.  This boundary level isn’t just a matter of convenience; our tools and methodologies for both implementation and verification can only deal with certain levels of complexity, so we are confined in many dimensions in how we can pursue finer granularity.

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Predictions 2013 – Ravi Ravikumar on Timing and Power

Monday, February 11th, 2013

 

 

 

Today’s prediction comes from Ravi Ravikumar, Vice President of Marketing at ICScape Inc. Ravi, who has over 18 years of experience in marketing, business development & project/program management in the EDA and semiconductor industries, gives his two cents on timing and power closure for 2013…..

 

“If you think timing and power closure were difficult issues at 40 and 28nm, they are going to get worse at 20nm. The traditional means of addressing timing/power closure as a post-implementation step using custom scripts that call on sign-off STA and physical implementation tools to achieve closure is taking too many iterations at 28nm.

As geometries reduce below 28nm, timing/power are more difficult to close due to design-related complex physical requirements, process and manufacturability issues like double/triple patterning and VT cell spacing rules create more R/C effects, impacting timing and power. Power issues in-turn lead to temperature and reliability problems. Design closure becomes a multi-dimensional task.

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Yet another 2010 EDA Trends write up?

Monday, January 18th, 2010

2009 was a rough year for an already stagnant EDA world. Looking to 2010, Liz Massingill and I asked industry colleagues, opinion makers and friends what each of them saw as the BIG trend for 2010.

Here’s what they said.

Karen Bartleson, Blogger, The Standards Game, Synopsys
http://synopsysoc.org/thestandardsgame/

The big trend in EDA for 2010 will be the acceptance of social media as an additional means for communicating with customers, partners, and competitors.

Now that blogging is settling in as a viable source of information from media people, company experts, and independent publishers, more new media tools will come into play. Not all tools are right for everyone or every situation, so the EDA industry will explore the options and experiment with a variety of community-development activities.

LinkedIn and Facebook will offer special interest groups a place to congregate. Twitter will be tested by more people – who today are curious or skeptical – as a means of immediate, brief interaction. EDA suppliers will offer new communication channels and those that are truly value-add will thrive.

The EDA world won’t change overnight, but the trends in social media will be noticeable.

Graham Bell, Director of Sales and Marketing, EDACafe
http://www10.edacafe.com/blogs/grahambell/

The BIG trend will be that designers need ALL of the technology that EDA companies have been working on and introduced in the last 18 months.

There is a lot of design work being done at 45nm and all the established tools are running at the edge of their capabilities.

New generations of parasitic extraction, static and statistical timing analysis, and automated property verification are just some of the important technologies that will be needed by design teams.

Mike Gianfagna, Vice President, Marketing, Atrenta, Inc.
http://www.atrenta.com

In 2010, we’ll see an accelerated move to doing more design at higher levels of abstraction.

Chip complexity and the skyrocketing cost of physical design, along with the advent of 3D stacks is forcing this. Designers just won’t be able to iterate in the back end in 2010 and beyond. It’ll take too long and cost too much.

Power management, design verification, design for test and timing closure will all be “close to done” before handoff to synthesis and place & route. The traditional backend flow of IC design will become a more predictable, routine process, which will accelerate its trend toward commoditization and consolidation.

This move to higher levels of abstraction will also have implications for IP selection and chip assembly. This will compel a new genre of tools to emerge. Standards like IP-XACT will help this process to take hold. Perhaps this is what ESL will become.

Richard Goering, longtime EDA editor and currently manager of the Cadence Industry Insights blog
http://www.cadence.com/Community/blogs/ii

I think the Big EDA Trend for 2010 will be SoC integration.

There will be a renewed focus on the challenges of integrating existing IP, providing breakthrough technology for design teams to quickly and reliably
assemble complex SoCs from integration-ready IP blocks, and then run
full-chip verification including both analog and digital components.

ESL is part of this story because there’s a need to move to
transaction-level IP creation, verification and integration. Hardware/ software integration and verification and will also become part of
the drive towards SoC integration.

Harry Gries, the ASIC Guy, EDA blogger
http://theasicguy.com/

As for the EDA trend in 2010, I think that EDA companies, when they recover, will choose not to hire more sales and marketing people but will invest more in other marketing tools on the Web or using social networking strategies.

A good example is a company like Xuropa, which is actually a client of mine, under full disclosure. They help EDA companies put their tools on the Web in order to help them reduce their costs for demos, product evaluations, etc.

I think that will see a lot of interest in the upcoming year as companies look for ways to do “more with less”. User group events may also move online, just like this year’s CDNLive was a virtual event rather than a real live event. Xilinx and Avnet sponsored an X-Fest this year that was also an online event. Things are moving online fast and economics will drive that.

Grant Martin, EDA blogger
http://www.chipdesignmag.com/martins/

In 2010, we’ll see the steady progress towards usable ESL tool and methodology adoption by design groups.

The areas of greatest real ESL use are the high level synthesis of data crunching blocks used in various DSP-type applications (signal and media processing), the increasing adoption of processor/SW-centric design methods, and the increased creation and use of virtual prototype models.

(Brian Bailey and I have a new book from Springer coming out in the new year on practical ESL use methods: “ESL Models and their Application: Electronic System Level Design and Verification in Practice”. See for a summary. )

Dan Nenni, EDA blogger
http://danielnenni.com/

For EDA, 2010 will be the year of the foundry. Foundries will drive new EDA flows and business models.

The TSMC Open Initiative Platform
is but the tip of the iceberg. If EDA and IP companies do NOT join forces with the foundries and take arms against the sea of semiconductor troubles – they will continue to suffer the slings and arrows of outrageous economic misfortune.

Coby Zelnik, CEO, Sagantec North America, Inc.
http://www.sagantec.com

In 2010, we will see more designs taping out in 40nm.

In an effort to minimize risk, cost and time to market, design reuse will be
maximized; many of them will be migrations of existing 90nm and 65nm products or derivative products with minor updates and tweaks.

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