Today’s prediction comes from Ravi Ravikumar, Vice President of Marketing at ICScape Inc. Ravi, who has over 18 years of experience in marketing, business development & project/program management in the EDA and semiconductor industries, gives his two cents on timing and power closure for 2013…..
“If you think timing and power closure were difficult issues at 40 and 28nm, they are going to get worse at 20nm. The traditional means of addressing timing/power closure as a post-implementation step using custom scripts that call on sign-off STA and physical implementation tools to achieve closure is taking too many iterations at 28nm.
As geometries reduce below 28nm, timing/power are more difficult to close due to design-related complex physical requirements, process and manufacturability issues like double/triple patterning and VT cell spacing rules create more R/C effects, impacting timing and power. Power issues in-turn lead to temperature and reliability problems. Design closure becomes a multi-dimensional task.
Our next prediction comes from respected blogger, consultant and software architect, algorithm, EDA and cloud computing expert, Olivier Coudert.
Olivier Coudert
In 2013, one major semiconductor company will use the services of a third party to offload its computing resource requirements (for synthesis, simulation, signoff, shared project, or anything they deem important) to the cloud. This third party will work with EDA vendors and cloud providers to build virtual design centers, where customers are given the means to develop, test, and sign off their product. And when I say “cloud” I mean major players in the cloud computing market.
Some semiconductor companies have been feeling the pain of capital investment in datacenters they only need at peak hours. So those companies are getting smart and will work with third party companies to access virtual design centers, build on demand, and pay as-they-go.
Soon any startup will have access to the computing resources and the EDA software they need to focus on innovation without breaking the bank. A new model for hardware startups, which the VCs will love. You will no longer need $10M to fund a hardware company, just a few $100Ks.
The next entry in our prediction series comes from Karen Bartleson, esteemed blogger, standards proponent, social media guru and Sr. Director of Community Marketing at Synopsys:
Karen Bartleson
2013 will be the year when people stop saying “engineers don’t use social media.” The data will show that indeed, they do use social media for both personal and work purposes. Not all engineers use it and some never will, but the way people live and work has changed. Engineers who are savvy about the modern ways that people communicate are seeing the benefits of incorporating social media into their regular activities.
The world did not come to an end in 2012, so we can now breathe a sigh of relief and prognosticate about 2013. Or can we? Well, we can but what sort of world will it be for the EDA and IP industries in 2013? Should we even go there?
We think so. So we asked industry friends, associates, clients and media folks to ponder what industry-shattering events or breakthroughs we might see in EDA & IP this coming year.
We’ll be posting predictions from these industry visionaries over the next couple of weeks. We hope that you will find them as enlightening and entertaining as we did.
We’ll begin with some eye-opening predictions by blogger, author and industry expert, Paul McLellan.
2013is all about lithography, EUV, the end of Moore’s law, 3D as a savior etc. Specifically:
• There will be a lot of discussion about the costs of 20nm since it is so much more than 28nm. It will be a very slow transition with some people going straight to 14/16nm (which is really 20nm with smaller transistors which is really 26nm with smaller transistors). Expect lots of discussion about the end of Moore’s law.
• EUV lithography will not become commercial during 2013 and so will miss the 10nm node.
• TSV-based 3D ICs will start to become mainstream. Memory on logic, and mixed digital/analog on interposer. Expect lots of discussion about “more than Moore” and how 3D is the new way for scaling.
• The death of a giant will finally take place. Nokia, still #1 only a year ago, will be dismembered. A consortium of Apple, Google and Samsung will buy the patents for billions. Huawei will buy the handset and base-station businesses for peanuts.
• Synopsys will acquire Mentor. EDA will otherwise be fairly boring with the big three being the only companies able to attack the upcoming problems that require dozens of tools to be updated, not just a new point tool inserted in the flow.
• If the IPO markets are open, Jasper, eSilicon, Atrenta and Tensilica will go public. If someone doesn’t buy them first.
In 2012, the industry discussed the qualities that reliable and reusable IP needs and the metric to measure those qualities. We think 2013 will be the year that the value of IP becomes tangible.
We tapped Warren Savage, CEO of IPextreme, to give us his thoughts on how to value IP.
Ed: So Warren, how do we figure out IP’s value?
Warren: In the most tangible sense, I think the question ought to be “how do we monetize IP?”
IPextreme has been at the forefront of this since we founded the company back in 2004, and it really was “extreme” back in those days to discuss licensing those “crown jewels.” But now it is increasingly mainstream and certainly the topic for industry discussion.
So one consideration revolves around the ton of licensing done in the industry today that is hidden. Primarily around patents and process technology. The transactional IP licensing that we specialize in, is really something that IPextreme invented.
Over the last couple of weeks we’ve been exploring the concept of stale IP – what it is and what to do about it. I’ve gotten insights from two industry experts in IP (Harrison Beasley of GSA and Manoj Bhatnagar of Atrenta). I will wrap up my series on this topic with one final view – from IP provider, Warren Savage, founder and CEO of IPextreme. He will challenge the whole idea of stale IP in this interview.
Liz: Stale IP – what is it?
Warren: Frankly, I’ve been working in IP for seventeen years, with most of the world’s largest IP and chip companies, and I have never heard the term before. I think people who think about IP being “stale” may be confused about the difference between IP and code. IP is certainly code, but code is not necessarily IP. I have argued vociferously for years on this topic, particularly opposing those who would claim that IP is a service business (see an old blog post by me “Repeat after me: IP is Product Business…” http://blogs.ip-extreme.com/2009/07/test-page.html). I think this notion of “stale IP” is sort of a regurgitation of the idea that there are classes of IP. For me, IP is something that is reusable indefinitely and valuable as long as there is a market for it.
In my last blog, Harrison Beasley shared his views on stale IP. This week we hear from Manoj Bhatnagar, Senior Director, Field Delivery and Support at Atrenta.
Liz: Manoj, what is stale IP?
Manoj:An IP may become stale because either its specifications have changed (e.g., USB 1.0 vs. 2.0 vs. 3.0) or there is a better implementation available (e.g., a graphics core is now running at 800Mhz instead of 500Mhz). Typically, people will use the latest version, and the older versions are no longer used. So the stale IPs in this case will die a natural death. What is more challenging, however, is a specific IP developed for a specific project and, over time, no other project used it. So the IP becomes stale. Most of my answers will apply to this type of stale IP.
Liz: What’s so bad about it?
Manoj: The main issue with a stale IP is the fact that nobody really knows the details about it. If I were to use that IP, I would be putting my design at risk because I am now adding some logic to my design for which I don’t have all the information and can’t find anyone who can provide that information either.
Liz: How do we prevent it from being stale?
Manoj: One of the key things that can be done to prevent IP from going stale is to document the IP. I don’t know how many people still remember the TTL datasheets but when you looked at the datasheet, you got complete visibility into what that component did. The same concept can be applied to present day IPs, where you document various characteristics of the IP. For a hard IP, this may be the timing characteristics, physical profile, etc. while for a soft IP this may be timing constraints, clock domain information, testability profile and power profile.
Stale IP is beginning to rear its ugly head. It’s like having too many books on your bookshelf – always an issue in my house. Where do you put the new ones? Which ones do you keep? What do you do with the ones you don’t want to keep?
I (Liz Massingill) recently polled some experts in the industry to get their stance on stale IP. Over the next few weeks I’ll share their views with you.
I’ll start with Harrison Beasley, Manager of the Technical Working Groups at Global Semiconductor Alliance (GSA). Here’s what he had to say:
Liz: Stale IP – what is it?
Harrison: IP becomes stale when the underlying code is out of date. This could be due to changes in a specification, errors found in use, soft IP not being updated, etc. My assumption is that stale IP will not perform the task for which it was created.
Liz: What’s so bad about it?
Harrison: Using stale IP could lead to non-functional silicon, tape out delays, end product failures, etc.
Liz: How do we prevent it from being stale?
Harrison: For internal IP, code checks before layout, during timing analysis, during verification, and before final tape-out help ensure the latest IP version is used. For third party IP, similar rules apply, but the user must coordinate with the IP Supplier to ensure changes are promulgated to the user.
What are the challenges in managing semiconductor IP?
How can we solve IP reuse integration?
If you’d like to know the answers to these questions and others, check out this presentation by Michael Johnson of Atrenta from the Constellations 2012 conference.
Johnson succinctly defines soft IP quality and proposes a way for the industry to get to a soft IP quality standard.
IPextreme’s Silicon Valley IP Users Conference 2012 edition has become a must-attend event for IP vendors and users, much more than a private tradeshow for IPextreme and its customers. I sat down with Warren Savage, IPextreme’s founder and CEO, and McKenzie Mortensen, the company’s mar com manager, to talk about the conference and its role in the chip design world.
Ed: So we’re talking about Constellations 2012…the program drew informative and opinionated speakers! Definitely more than a private tradeshow. When did Constellations begin? What were your goals?
Warren: I think it was a hit precisely because it was not intended to be just another private tradeshow. The world has changed a lot since the 1990s.
Ed: Hmmm…you mean for the chip design world? How has it changed?
Warren: Well, I think it’s time that companies start evolving to better understand how to serve their customers in a way that is not hitting them over the head with sales pitches.
Ed: And that customer service attribute is one that vendors to chip designers have been notoriously lax about. Back in the late 1990s or early 2000s, I remember an analyst, it could have been Jennifer Jordan, wagging her finger at the EDA world on this count, while taking us to task for doing a bad job of selling the industry’s value to the public markets.
So how does the conference and your Constellations program change this?
