Archive for the ‘Uncategorized’ Category
Wednesday, June 13th, 2012
Ikutaro Kojima, editor of Nikkei’s Tech-On!, talked with ICScape at DAC about their products and their future plans for them. Here is the link and a rough translation of the article:
http://techon.nikkeibp.co.jp/article/NEWS/20120604/221364/
ICScape not likely to announce mixed-signal EDA until end of year [from DAC 2012]
2012/06/04 16:45
Ikutaro Kojima, Tech-On!
With the 49th Design Automation Conference ready to open tomorrow, I spoke with EDA vendor ICScape Inc (which was established in 2005) about its soon-to-be introduced mixed-signal EDA system.
The company exhibited at the 2011 January EDS Fair in January 2011 here in Japan. There, ICScape introduced back-end EDA tools for large SoC designs: e.g., for multi-corner multi-mode. Those tools are 1) “TimingExplorer,” for MCMM optimization use just before timing sign-off; 2) “ClockExplorer,” used to convert clock synthesis input to existing constraints (MCMM); 3) “Skipper,” which quickly reads huge GDS-II files; and 4) “RCExplorer,” a parasitic parameter extraction tool for analog/mixed-signal IC.
In January 2011, the same month as EDSF2011, ICScape merged with China EDA vendor Huada Empyrean Software (HES), developer of RCExplorer. The remaining three products were developed by ICScape in the pre-merger period. According to President Steve Yang, the merger is ideal and there is no post-merger overlap for products or customers. In other words, ICScape was primarily in the U.S. market for digital large-scale EDA tools, while HES was primarily in the Chinese market for analog EDA tools.
Based on OpenAccess
Both toolsets share the OpenAccess database as a platform. According to Mr. Yang, the two companies are integrating their tools into a mixed-signal IC EDA toolset: “We are developing a new system for EDA (analog-digital-mixed IC). It is almost complete, and is in the customer evaluation phase currently. We expect to formally announce this toolset in the second half of 2012.”
Aiming for big analog · small digital
ICScape will officially announce an integrated analog-digital EDA system later this year. This product is for “big analog · small digital” IC designs (where the digital circuit is a small majority of the IC that is mixed in with the analog). According to Mr. Yang, “big analog · small digital IC design is handled by one designer. These designers are asking for a single system.”
Mr. Jason Xing, Vice President of Engineering, says that the key to development of the mixed-signal EDA system was the realization that digital and analog design is not separated and that it needed to be OpenAccess based.
Jason Xing and Steve Yang
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NOTE: Lee PR does work for ICScape
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Tuesday, June 12th, 2012
Tags: 49DAC, DAC, Design Automation Conference, EDA, Electronic Design Automation, IP, IP libraries, migration, process migration, Sagantec, Semiconductor IP, Tech Design Forums
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Friday, June 1st, 2012
Atrenta has pulled together quite a slate of customers, partners, an industry observer and EDA’s premier investor to talk about the value SpyGlass brings to each of their realms. It’ll be interesting to hear how this signature product has proliferated in different environments! Atrenta invites you to stop by and hear how SpyGlass improves productivity @ Xilinx, Vivante, Sonics and Arteris and why Dan Nenni and Jim Hogan see SpyGlass as the consummate ubiquitous product in EDA.
The talks will be held at Atrenta’s booth #2230.
Monday, June 4
9:30 am…..Jack Browne, Sonics
10:30 am…Frederic Rivoallon, Xilinx
2:00 pm…..Halim Theny, Vivante
Tuesday, June 5
10:30 am…Charlie Janac, Arteris
2:00 pm…..Frederic Rivoallon, Xilinx
3:00 pm…..Dan Nenni, SemiWiki
5:00 pm…..Jack Browne, Sonics
Wednesday, June 6
10:30 am…Charlie Janac, Arteris
12:30 pm…Jim Hogan
……………………….
Note: Lee PR does work for Atrenta
Tags: 49DAC, Arteris, Atrenta, DAC, Design Automation Conference, EDA, Electronic Design Automation, investments, Jim Hogan, RTL, Sonics, SpyGlass, Vivante, Xilinx
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Thursday, May 31st, 2012
 I recently talked with Atrenta’s senior director of product marketing, Kiran Vittal, about power management/optimization trends and approaches that we’ll see at DAC next week.
Ed: So power, or rather more rigorous power management will be a hot topic at DAC. How come? What will be different this year?
Kiran: As we all know, power is of the biggest concern to both mobile applications as well as wired devices. An average mobile SoC is over 100M gates operating at over 500Mhz and designers do everything necessary to apply all known power management techniques to reduce power.
It will also be interesting to see that application processors for cloud-based servers are now being designed with over 10 power domains to shut off power in non operating regions and a quad core SoC consumes around 5 watts during maximum utilization and as little as 0.5 watts during idle time.
Ed: So what approaches are we going to hear about @ DAC?
Kiran: We are going to hear about power management, power intent creation using standards, power optimization, power verification and sign off.
Ed: How do they stack up?
Kiran: It is very clear that any power management and optimization technique applied at the gate level is too late to make any difference to the aggressive low power requirements. Early power planning, RTL power estimation, automated reduction around both registers and memories and early power intent verification is the only way to achieve today’s aggressive power goals for both mobile as well as wired chips.
Stop by Atrenta’s booth (#2230) to talk about Kiran’s views with him!
……………..
Note: Lee PR does work for Atrenta
Tags: 49DAC, Atrenta, DAC 2012, Kiran Vittal, power management, power optimization, RTL
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Friday, May 25th, 2012
Named by industry observers as “the biggest EDA company you’ve never heard of” and “a rare and endangered species” of EDA companies, ICScape will bolt out of stealth mode to exhibit at DAC for the first time.
Founded in 2005 by Steve Yang and Jason Xing, the company’s been busy over the last year. How? Merging with analog EDA vendor Huada Empyrean Software (HES), getting that US$28M infusion to fund global R&D, customer support and sales expansion, and working on OpenAccess-based product lines that we’ll probably see in some integrated form toward the end of 2012.
ICScape’s booth will greet attendees right at the entrance to the exhibit floor, in Booth 1602. The company’s executives will be there to:
1) talk about its technology,
2) introduce current customers (a major silicon valley Fabless IC company and a major Silicon Valley analog device company) who will also be available at the booth to share firsthand experience,…..and
3) ensure that ICScape will be one of the EDA names that all of you will have heard of.
See what Paul McLellan, Mike Demler and Brian Bailey have to say about ICScape:
http://www.semiwiki.com/forum/content/1248-biggest-eda-company-you-ve-never-heard.html
http://www.eedailynews.com/2012/05/examining-rare-and-endangered-species.html
http://www.eetimes.com/electronics-blogs/other/4372423/New-Companies-exhibiting-at-DAC—ICScape
See you at DAC!
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Note: Lee PR does work for ICScape.
Tags: A/MS, analog/mixed-signal, Brian Bailey, DAC, Design Automation Conference, design closure, EDA, EE Daily News, EE Times, Electronics Design Automation, Finance, HES, Huada Empyrean, IC, ICScape, integrated circuits, Mike Demler, Paul McLellan, SemiWiki, SoC, SoC design, System on Chip
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Tuesday, May 15th, 2012
Maybe Atrenta is saying goodbye to the thought-bubble guy…..
Atrenta’s SpyGlass has always been the dominant name in the company’s brand portfolio,and for good reason. It’s the dominant product in RTL design analysis, verification and optimization.
Now, Atrenta is reconfiguring its product lineup to formalize this state of affairs. SpyGlass now becomes the unifying platform for all Atrenta products. Sort of the mother ship that all Atrenta products are based on.
So what’s a unified platform? All the tools now share a common set up and debugging methodology and tighter GUI. And what can users verify and optimize from this new unified platform? Syntax, power, testability, clock synchronization, timing and routing congestion. All at the RTL stage, well before detailed implementation begins.
(more…)
Tags: 3D IC, Atrenta, Chip Design, DAC, DAC 2012, Design Automation Conference, EDA, Electronic Design Automation, GUI, IP quality, RTL, SpyGlass
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Thursday, April 12th, 2012
 Take a look at Karen Bartleson’s interview here!
http://www.eeweb.com/pulse/issue-41-2012
While we all know Karen as the standards guru at Synopsys, her story on how she got here – and next year, to the Presidency of the IEEE Standards Association – speaks to her resolve, smarts and diplomacy.
Interestingly, her engineering education experience speaks to San Jose State engineering dean Dr. Belle Wei’s thoughts on women in engineering. That “back in the day” (which is another way of saying no years allowed here) women engineering majors peaked in number, and have fallen since.
Seems to me that it’d be a fascinating interview: Bartleson and Wei on this topic…why it’s dropped and what to do about it.
One suggestion on the article: EEWeb could have included a picture of Karen’s yellow Camaro. Maybe she’ll drive it to DAC this year! You’ll know that Karen is a-coming when you see the car in the pictures below.
Tags: Belle Wei, College of Engineering, DAC, EDA social media, EDA standards, IEEE Standards Association, Karen Bartleson, San jose State, Synopsys community marketing, women in engineering
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Thursday, March 29th, 2012
This event is happening next week! Worth signing up if you can get down
there!………
EDPS is coming up again! It’ll be held April 5-6, 2012 at the Monterey Beach Hotel in Monterey California.
This year, the 3D topic will be the focus of day two.
First and foremost, Riko Radojcic, director of engineering at Qualcomm, will be talking about the 3D IC roadmap as the keynote speaker on day two. (see his views on 3D standards: http://www10.edacafe.com/blogs/ed-lee/2011/04/11/riko-radojcic-on-3d-standards/
Following the 1-hour keynote will be four 1/2 hour talks on various specific 3D-related topics:
* Stephen Pateras of Mentor on BIST for 3D ICs
* Arif Rahman of Altera on FPGA design challenges, presumably 3D ones
* Marc Greenberg of Cadence on the wide-IO standard for putting memory stacks on processors
* Sandeep Goel of TSMC and Bassilios Petrakis of Cadence on an end-to-end test flow for 3D IC stacks
Then there’s a lunch panel on 3D, moderated by Steve Leibson of Cadence, with these panelists addressing: The short-, medium and long-term path to the 3D Ecosystem.
* Herb Reiter
* Samta Bansal of Cadence
* Dusan Petranovic of Mentor
* Deepak Sekar of Monolithic 3D
* Steve Smith of Synopsys
* Phil Marcoux of PPM Associates
Herb is arguably the primary 3D observer and advocate on what technologies have to be in place to handle the upcoming 3D challenge that’s starting to hit designers now.
John Swan is the General Chair of EDPS 2012. Herb Reiter is the Session Chair for the keynote, four shorter presentations and the panel discussion during “3D Day”, Friday, April 6.
Very worthwhile to attend if you can get the time off.
Tags: 3D, 3D Ecosystem, 3D IC, Altera, Arif Rahman, Cadence, Chip Design, chip designers, DAC, Deepak Sekar, Dusan Petranovic, EDA, eda 2 asic Consulting, EDPS, Electronic Design Automation, Electronic Design Process Symposium, Herb Reiter, IEEE, John Swan, Marc Greenberg, Mentor, Monolithic 3D, Phil Marcoux, PPM Associates, Riko Radojcic, Samta Bansal, Sandeep Goel, semiconductors, Stephen Pateras, Steve Leibson, Synopsys, TSMC
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Tuesday, March 27th, 2012
All of us in EDA know and know of Graham Bell, head honcho of EDA Café and notorious video chronicler of EDA. Liz and I often wonder, “who hasn’t Graham interviewed on video?”
Well, we were able to grab the microphone (after a little jostling for the mike) and camera and ask Graham what he thought was happening in EDA and with EDA media these days.
Here’s what he had to say.
Tags: EDA, EDA bloggers, EDA Cafe, EDA media, EDA press, EDA trends, Graham Bell, http://www.leepr.com, Lee PR, state of EDA
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Thursday, March 22nd, 2012
EDPS is coming up again! It’ll be held April 5-6, 2012 at the Monterey Beach Hotel in Monterey California.
This year, the 3D topic will be the focus of day two.
First and foremost, Riko Radojcic, director of engineering at Qualcomm, will be talking about the 3D IC roadmap as the keynote speaker on day two. (see his views on 3D standards: http://www10.edacafe.com/blogs/ed-lee/2011/04/11/riko-radojcic-on-3d-standards/
Following the 1-hour keynote will be four 1/2 hour talks on various specific 3D-related topics:
* Stephen Pateras of Mentor on BIST for 3D ICs
* Arif Rahman of Altera on FPGA design challenges, presumably 3D ones
* Marc Greenberg of Cadence on the wide-IO standard for putting memory stacks on processors
* Sandeep Goel of TSMC and Bassilios Petrakis of Cadence on an end-to-end test flow for 3D IC stacks
Then there’s a lunch panel on 3D, moderated by Steve Leibson of Cadence, with these panelists addressing: The short-, medium and long-term path to the 3D Ecosystem.
* Herb Reiter
* Samta Bansal of Cadence
* Dusan Petranovic of Mentor
* Deepak Sekar of Monolithic 3D
* Steve Smith of Synopsys
* Phil Marcoux of PPM Associates
Herb is arguably the primary 3D observer and advocate on what technologies have to be in place to handle the upcoming 3D challenge that’s starting to hit designers now.
John Swan is the General Chair of EDPS 2012. Herb Reiter is the Session Chair for the keynote, four shorter presentations and the panel discussion during “3D Day”, Friday, April 6.
Very worthwhile to attend if you can get the time off.
Tags: 3D, 3D Ecosystem, 3D IC, Altera, Arif Rahman, Cadence, Chip Design, chip designers, DAC, Deepak Sekar, Dusan Petranovic, EDA, eda 2 asic Consulting, EDPS, Electronic Design Automation, Electronic Design Process Symposium, Herb Reiter, IEEE, John Swan, Marc Greenberg, Mentor, Monolithic 3D, Phil Marcoux, PPM Associates, Riko Radojcic, Samta Bansal, Sandeep Goel, semiconductors, Stephen Pateras, Steve Leibson, Synopsys, TSMC
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