Real RTL Signoff™ is a Comprehensive Signoff

RTL Signoff is certainly one of the hot topics in chip design circles lately, and one that is garnering great interest and concern.  I chatted recently with Piyush Sancheti, VP of Marketing at Atrenta, on what it is, why it’s a design imperative, and how it should be done.

Liz:  Piyush, thanks for taking the time out to chat with me today on this vital topic…RTL Signoff.

Piyush:  No problem, Liz

Liz:  So, to start out, what is RTL Signoff?

Piyush:  “RTL Signoff” gained momentum as an established concept in 2013. While the concept is not new, a commonly-accepted definition did not exist in the past, which is now beginning to emerge.  Here’s what I think RTL Signoff is: a comprehensive series of well-defined MUST-pass requirements for your RTL before you commit the design to downstream implementation such as synthesis and physical layout. In addition to this complete set of RTL Signoff requirements, you need tools and methodologies to meet the requirement, along with tangible metrics to measure your pass/fail criteria.

Liz:  What do you mean by “comprehensive?”

Piyush:  I’m talking about a comprehensive list of MUST-pass requirements spanning robustness of RTL across a wide range of structural, functional and implementation issues.

Liz:  What’s on the list?  

Piyush:  Functional coverage signoff, including high quality assertions; clock domain crossings, including static and dynamic verification; timing constraints, including false and multi-cycle path verification; power consumption, power intent (UPF) verification; test signoff, including stuck-at and at-speed coverage; physical signoff, including routability, area, and timing. And I expect this list to expand as RTL Signoff gets wider industry adoption.

Liz:  What has changed in today’s SoC design to require this RTL Signoff mandate?

Piyush:  There’s been a huge explosion in design complexity resulting from the hyper-integration of multiple functions on a single chip. We see that entire PCBs or systems are now being replaced with a single SoC. To manage this complexity, SoC designers are increasingly reliant on externally-sourced semiconductor IP, both from 3^rd party suppliers and from other design groups within the company. Typically this IP is delivered as user-configurable RTL, which then gets configured for the SoC needs and subsequently integrated. What used to be a lot of design from scratch now is integration of these RTL IP blocks, which makes it extremely critical that they be signed off before integration into the SoC.

Liz:  In cases like that, where the SoC replaces an entire PCB, what does that mean to the SoC?

Piyush:  A surge of functionality (computing, audio, video, wireless, gaming, external interfaces, memory interfaces, power management, etc.) is crammed into a single chip the size of your thumbnail. We are beginning to see SoC designs with more than a billion gates. This is a staggering task…to ensure that all SoC functions work seamlessly…that the device can be manufactured reliably, is cost effective, has hours of battery life, and responds instantly to your every command.  So the question is: how does a designer ensure that all of this will work?

Liz:  This sounds quite overwhelming.

Piyush:  Liz, it IS overwhelming.  Along with this explosion in design complexity, we now have very short market windows and shrinking product cycles – sometimes windows are as short as 3-6 months. A miss on such tight windows can jeopardize the entire project. As you can see, there’s a burning need to manage this risk, which, as I said before, is driving increased reliance on 3^rd party IP and internal IP reuse.

Using proven IP content reduces content design risk, but there’s still the risk in assembly and “spec” compliance. IP is not quite plug-and-play yet. They are open to bugs, misuse, abuse and surprises when used outside tested configurations. Any of these issues can derail a project schedule.

Liz:  So, how can RTL Signoff rescue today’s chip designer?

Piyush:  Let me answer it backwards by saying that the benefit is that it can contribute up to 60% reduction in the design risk.

Liz:  How so?

Piyush:  RTL tools run faster than layout tools. This allows you to find and fix a lot more problems at RTL, per unit of time, than you can at synthesis or layout. What’s more, higher quality RTL reduces risk of iteration from synthesis or layout back to RTL. And as we all know, a restart of design layout is very expensive. We have customer data that estimated schedule risk on a high-end SoC at more than one year, so a 60% reduction does get their attention.

Liz:  What other ways can RTL Signoff help the designer?

Piyush:  RTL Signoff can be applied very effectively to IP, both internal and external. Since most IP is sourced as RTL, signoff checks can and must be enforced as part of handoff requirements from the IP supplier, AND as acceptance checks by the SoC team. When dealing with configurable IP, acceptance checks by the SoC team for the configuration you want to use becomes all the more important. Trust but verify.

If your design team employs a rigorous IP signoff methodology at RTL, you get significant efficiencies for SoC level RTL Signoff. At the SoC level you must validate assumptions in the IP and make necessary tweaks when the two are not in sync. Once those are validated, the SoC level signoff can focus on IP integration and commonplace issues at the top level. Then it’s not necessary to validate the internals of IP at this stage, as long as you can intelligently abstract IP validation models. Abstraction can drive an order of magnitude improvement in analysis time and hardware requirements. Ultimately this leads to a significantly-simplified signoff flow.

Liz:  Any final thoughts you’d like to add?

Piyush:  I’d say that for 2014, RTL Signoff is no longer a choice … It’s a design imperative! Leading-edge SoC design teams have been practicing and reaping the benefits of RTL Signoff for some years now, and it is now present in mainstream SoC design flows. If you are not doing it, you should be! Selective checklists are not a substitute for a comprehensive and disciplined approach. You wouldn’t sign off layout with selective checks…. just as you wouldn’t drive a car on three tires. It’ll probably work but it’s not a guarantee that you’ll get where you want to go. So, you shouldn’t accept anything less than comprehensive RTL Signoff.

Liz:  Thank you, Piyush, for alerting us to the crucial need for comprehensive RTL Signoff.

Lee PR does work for Atrenta

Tags: Atrenta, Chip Design, EDA, EDA & IP, Electronic Design Automation, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, Intellectual property, IP, Piyush Sancheti, register transfer level, RTL, RTL signoff, Semiconductor IP, semiconductors, SoC, System on Chip, www.leepr.com

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