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Archive for May 14th, 2013

IP up front at DAC

Tuesday, May 14th, 2013

These two trend setters share their opinions on the BIG DAC themes in 2013.

I see two related trends:

1) More signoff activity earlier in the design flow

2) More focus on IP quality and usability

Both of these trends represent a maturing of design tools and business models. Because of the tremendous complexity that sub-20 nm design brings, it becomes more important to get the design right as early as possible. The tools are maturing in the earlier stages, and more designers are demanding clean reports, or sign-off level quality audits as a result.  This is helping to reduce schedule delays and design costs – good for the industry.

Semiconductor IP is also maturing – both use models and business models.  There is a growing focus on reporting delivered quality and robustness.  This will allow IP providers that deliver the best IP to flourish.  Also good for the industry.  We’ll see an increase in conversations about IP providers collaborating with the rest of the ecosystem at DAC.  Another good trend.

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What’s the BIG theme for DAC50?

Tuesday, May 14th, 2013

DAC is upon us….and in Austin, of all places – the island in the middle of Texas.

As it’s getting closer, we were wondering what the BIG theme is for the 50th DAC.  So, we asked a few of our friends and colleagues in the industry.  Here’s what a few of them had to say.

 

I expect DAC to continue to explore low power challenges, with much talk about solving FinFET issues at 14 and 10 nm. Then there is the ever expanding SoC and how to handle all of the challenges that come with greater integration and IP reuse. Finally, what’s DAC without a discussion of Moore’s Law and whether it will/won’t continue to define industry progress in the years to come?

~ Joe Desposito, Editor-in-Chief, Electronic Design

 

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