I attended Qualcomm, imec and Atrenta’s presentation to bloggers on 3D this afternoon and it was enlightening to hear about what this up and coming design approach could give a company like Qualcomm.
Qualcomm’s Riko Radojcic clearly was the point person on the joint effort. After all, he was the customer specifying what his intriguing PathFinding vision and technology had to be and become….and he’s been working on this for QUITE a while. Radojcic noted that while the promise of 3D is high and sets expectations about a new level of design, the reality is that the technology to achieve 3D design is broken. That’s how he embarked on the definition and realization of Qualcomm’s PathFinding vision and technology. He heads up the Qualcomm PathFinding technology effort.
Atrenta, imec and AutoESL collaborated to create what Qualcomm thinks is the first working 3D flow. While it’s incomplete – only HLS and early estimation tools are included right now – Radojcic said it has started him on realizing the PathFinder vision. He said that he certainly needs HLS and early estimation tools and that gets him started. He needs early estimation to find the sweet spot for a chip’s architecture and the technology for those leading edge designs Qualcomm designs. BUT this first version of the flow will need more tools and a lot of support by the time the 3D design demand hits in 2012.
The presenters kicked off the event by defining what 3D is. They agreed that with 3D design, you mix and match into one vertical step. Easy, right? Well, not quite. All of them recognized that the complexities of 3D require that you get it all right up front. And that is harder than anyone thinks.
The presenters agreed that a lot of work needs to be done to realize Radojcic’s PathFinding vision, of which 3D is a big part. But the tool vendor partners also saw it as an opportunity for them and the EDA vendors as well.
– Liz Massingill
This acquisition puts Synopsys squarely in the front of the pack as far as IP suppliers go. This trend could be quite significant. Successful IP reuse is a combination of the right EDA tools, best practices methodology and well-designed IP. The EDA vendor is a pretty good place for all that to come together. ARM remains the exception to this rule, and several other rules for that matter.
I don’t see how this doesn’t make Synopsys a competitor with ARM on physical IP and ARC processor. ARM should start feeling like it is getting surrounded by Synopsys.
With EDA trying to expand its scope and grow beyond its traditional boundaries (see EDA360), and with small and medium size IP vendors struggling to grow, basic economy forces are pushing this trend.
Mike Gianfagna, well known and long time EDA executive, has quite a bit to say about the EDA360 manifesto that’s electrified the EDA world. As vice president of marketing at Atrenta, Inc, Mike has been an astute, articulate participant in the EDA value discussion. I was able to grab a few minutes with Mike to ask how EDA360 helped define the 2010 and beyond definition of EDA value and how it might alter the industry’s direction.
