Posts Tagged ‘Synopsys’
Monday, May 23rd, 2016
I just wanted to take a moment to personally invite you to attend Synopsys’ Custom Compiler lunch event at DAC 2016 on Tuesday, June 7 in Austin, TX. At this event, engineers from GSI Technology, Samsung, STMicroelectronics, and Synopsys’ IP Group will showcase their experiences using the new Custom Compiler custom IC design tool with Visually-assisted Automation technologies.
As you’ll recall, Synopsys unveiled Custom Compiler on March 30 of this year at SNUG Silicon Valley. Custom Compiler is a new custom IC design solution that closes the FinFET productivity gap by cutting custom layout tasks from days to hours. It offers a fresh approach to custom design that employs Visually-assisted Automation technologies to speed up common design tasks, reduce iterations and enable reuse. Visually-assisted Automation technologies are a unique set of productivity aids that leverage the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints.
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Tags: Custom Compiler, custom IC design, DAC 2016, FinFET, layout, SNUG, Synopsys, visually-assisted automation
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Wednesday, March 30th, 2016
Over the last few blogs I have outlined some of the productivity challenges that the FinFET process brings with respect to custom layout. Today Synopsys unveiled Custom Compiler and ushered in a new era of visually-assisted automation. Custom Compiler has all the good stuff I’ve been saying is needed in earlier posts: a new custom design solution that closes the FinFET productivity gap by shortening custom design tasks from days to hours.
This is not a revamp of the old constraint-based legacy approach, it’s a fresh approach to custom design that employs visually-assisted automation technologies to speed up common design tasks, reduce iterations and enable reuse.
What’s visually-assisted automation, you may ask?
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Tags: constraints, Custom Compiler, custom design, DRC, electromigration, EM/IR, FinFET, layout, SNUG, StarRC, Synopsys, visually-assisted automation
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Monday, March 28th, 2016
What tools do we have in our FinFET toolbox that can help layout engineers manage the complexity that FinFETs inherently bring?
Well for my money, the best and most powerful tool we have to tackle FinFET complexity is the good old parameterized cell or PCell. PCells are not new, they have been around since the CALMA GDS days and along with Schematic-Driven Layout, have been instrumental in boosting layout productivity, as I have mentioned in my previous posts. PCells have typically been used to generate physical layout of pretty much all the devices needed for custom layout, from resistors to inductors, capacitors and, of course, the transistor. That is still the case for FinFET designs; however the role of the PCell has now been expanded to include the schematic PCell.
So what’s the big deal about a schematic PCell, you might ask? And why didn’t we have them before?
Well, some companies did use schematic PCells, but mainly to generate symbols. With FinFET there are many more reasons that a schematic PCell should be used. It boils down to three things: complexity, aesthetics, and productivity.
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Tags: custom design, FinFET, PCell, Schematic PCell, Synopsys
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Friday, March 18th, 2016
Continuing on the theme of FinFET layout, let’s consider what you have to do for routing. Again drawing on the experience of my layout colleagues who are still ‘in the business’ and dealing with FinFETs, here are a few landmines you will have to deal with.
One particular issue they encounter is that although the base layers have shrunk considerably, the shrink of the routing layers has not kept pace. Each new node has brought us smaller transistors, but the minimum metal pitch has not really changed. This really impacts layout floorplanning because designs that were once dictated by device area are now dictated by the ability to route the required signals. Double-/triple-patterning compounds the issue even further.
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Tags: electromigration, EM, FinFET, floorplanning, IR, layout, planar, routing, Synopsys, topology
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Wednesday, February 24th, 2016
In my last post, I said: “A hurricane has made landfall and its name is FinFET”. OK, it’s a little corny, but it was not meant to convey a sense of impending doom for custom layout productivity. No question that hurricanes are disruptive, but humans can adapt to even the worst nature can bring. And FinFETs bring tremendous benefits along with the disruption.FinFETs are without doubt the most radical shift in semiconductor technology in decades, but moving to FinFETs is absolutely necessary. As feature sizes became finer, high leakage current due to short-channel effects threatened to put the brakes on scaling. FinFETs address the leakage issue and give Moore’s Law a new lease of life.Today the bulk of design starts are at the established nodes above 28 nm, so not everyone doing custom layout has experience with FinFETs. For those who have not yet felt the ‘winds of change’ that FinFETs bring, here is a brief primer.
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Tags: 3D, custom design, EDA, FinFET, layout, Moore's Law, MOSFET, planar, SoC, Synopsys, UC Berkeley
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Monday, February 15th, 2016
I left off in part 2 of this blog asking the question: “Have we exhausted all avenues in our search for layout productivity?”
Although there has been no revolutionary technology as with the initial CALMA systems, there have been some incremental improvements that help oil the gears when doing layout.
On-line DRC has been one such improvement. Having the ability to check the layout for design rule violations incrementally, as you complete more and more of the design, made it easier to implement changes. Violations were displayed in the layout, making it easy to find and fix them. However, checking the layout connectivity versus the schematic was still a batch task that could only be run when the design was fully implemented. The connectivity of the physical layout had to be extracted in order to compare against the logical connectivity.
As EDA marched on, with each new crop of more powerful workstations came the next generation of interactive tools. If you could compute the design rule checks fast enough, why not show them dynamically as layout geometries were being created? And so Design-Rule-Driven (DRD) layout was born.
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Tags: analog, CALMA, CMOS, custom design, DRC, DRD, EDA, FinFET, IC, layout, routing, SDL, SoC, Synopsys
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Wednesday, February 10th, 2016
If I say ‘sticks’ to you, what comes to mind? Well, you could reply with “bits of wood” or “an American rock band from the 70’s” or “a river in Hades” and you would be correct. However, when you ask the question in the context of EDA, well, that’s a different story.
‘STICKS’ or ‘stick diagrams’ refers to a technology called symbolic layout. My first introduction to symbolic layout was the CALMA STICKS package that emerged around 1983.
STICKS was a netlist-driven symbolic design package that produced correct-by-construction physical layout directly from the logical netlist. Although a great concept, it never really took off. The effort to bring the logical connectivity into the layout by means of a netlist did not deliver a high-enough ROI in the eyes of the layout community.
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Tags: analog, correct-by-construction, custom, EDA, IC, schematic-driven layout, SDL, SoC, STICKS, Synopsys
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Thursday, February 4th, 2016
It’s amazing what you find when you clean out your garage. I came across some old photographs of the first CALMA systems I worked on. Boy, have we come a long way since those days!
Those early CALMA Graphic Data Station (GDS) systems that I worked on back in the late 1970s were considered revolutionary. Why revolutionary? Well before they came along, making the masks for an IC was a real pain. Here’s a brief recap of what you had to do to:
Before GDS, the IC layout engineer would have to draw the circuits on large sheets of grid paper, using a different color for each layer of the circuit. Then they would produce a mask of each layer by cutting the shapes into a peel coat material such as Rubylith. To get a rectangle for example you would cut the four edges that made up the rectangle through the top layer of the Rubylith but not through the base layer. The peel coat material would be removed, leaving the rectangle exposed. The sheets were then photographically reduced to the real size of the IC. A stepper was then used to produce the physical masks by replicating the sheets as many times as would fit on a mask that was the real size of the wafer. Typical wafer sizes back then were around 4 inches. As you can imagine, this was very time consuming and very error-prone.
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Tags: analog, custom design, IC, Synopsys
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