Posts Tagged ‘analog’
Thursday, January 12th, 2017
Happy New Year!
There’s no doubt that FinFET technologies have been very appealing. With FinFETs being up to 37% faster while using less than half the dynamic power than planar transistors, they have been a ‘no brainer’ to adopt and the industry has embraced them. To that extent, in a recent survey of Synopsys users, more than a third of those who responded plan to use FinFET technologies on their next chip.
Since its introduction, the technology has been rapidly evolving. Take TSMC, for example.
TSMC’s 16FF+ (FinFET Plus) technology features FinFET transistors with a third-generation High-k/Metal Gate process, a fifth generation of transistor strain process, and advanced 193nm lithography.
As a result, this latest 16nm technology offers substantial power reduction for the same chip performance. Now foundries are pushing even lower into 10nm and even 7nm process geometries.
In previous blog posts I outlined some of the many challenges that the first generation of FinFET technologies introduced into the custom layout flow. Many of you will be hitting these issues for the first time as 16nm and 14nm technologies move into the mainstream. For those moving beyond the 16/14nm generation, there is trouble ahead as a whole new set of issues must be overcome.
For nodes below 16/14nm we see new challenges related to design rules, layout effort, variation and analog/digital co-design. So over the next few weeks I will unfold the gory details of these emerging challenges.
Here’s hoping 2017 is a productive year for us all as we meet our challenges head-on!
Thursday, December 1st, 2016
In the last blog post I profiled the use of Custom Compiler’s Symbolic Editor for rapid digital cell layout.
In this post, we will tackle analog cell layout and show some more of the Symbolic Editor features that enable analog layout engineers to complete their layout in minutes vs. hours.
As with the digital cell layout, engineers can take advantage of the Symbolic Editor’s ability to define multiple P and N row pairs, as shown in Figure 1.
Figure 1. Multiple Row Pairs
The preview window shows how the layout will look when realized on the layout canvas. In this example, it is clear that in order to make the design more compact, the larger transistors need to be folded.
Folding the transistors is very easy using the Symbolic Editor. Options on the toolbar allow the designer to fold the transistor by specifying either the number of segments desired or by specifying a width threshold. Once the option is set, all the layout engineer has to do is simply select the appropriate devices and have them folded such that the transistors fit neatly in the rows. Figure 2 shows how the design looks before and after folding.
Thursday, November 3rd, 2016
In the ‘Custom Compiler Layout Assistants (Part 1)’ blog post, I profiled the use of the symbolic editor and how it makes placing devices that need to be in a specific interdigitated pattern (for example, a differential pair) very easy. With no constraints to enter and no code to write, layout is done in minutes vs. hours.
However, there is a lot more to the symbolic editor than the ability to simplify interdigitation. One good example is the ability to define multiple P and N row pairs and then symbolically chain and fold the transistors such that you get them to fit neatly in the rows. This is a key feature that allows you to not only control the aspect ratio of the design, but to very rapidly create a custom digital cell layout, as shown in Figure 1.
Figure 1. Multiple Row Pairs
Tuesday, May 10th, 2016
Over the last series of blogs we have looked at which tools the layout engineer has available to him/her to help deal with the complexity of doing layout with FinFETs. Even though there are tools that help, the fact is there is still a productivity hit when comparing the time it takes to do a FinFET-based layout vs. a planar CMOS layout. When I asked my layout colleagues “How much longer does it take to do a FinFET-based design vs. planar CMOS?”, they said it takes 2-3X longer.
So, if we are to recoup layout productivity when doing a FinFET-based design, which areas should we focus on? Well, let’s start at the very beginning, which, according to Julie Andrews in The Sound of Music, is a very good place to start. The task of generating the devices and placing them such that they meet all the design rules and will produce a robust working design is about 30% of the layout time. So if we can speed up this task then we will gain back some of the productivity we lost due to the complexity of the FinFET process.
Wednesday, March 9th, 2016
So, FinFETs rule! They give the designer so much flexibility in trading off power and performance that it should be a no-brainer to adopt the technology–right?
Well, every silver lining has to have a cloud, and in the case of FinFETs there are quite a few.
I polled a number of layout designers who have first-hand experience of laying out FinFET designs and asked them “What’s the impact of FinFET?”. Here’s what they told me requires them to do extra work:
- First off is the sheer number of rules that they have to be conscious of. The number of rules has more than doubled compared to a 40-nm process. Of special concern are some of the density rules that now have to be applied to a lot more layers.
- Another area you have to pay particular attention to is maximum diffusion space. This forces devices to have guardrings around them so that you do not have too large a diffusion space. The diffusion in the guardring essentially breaks the space check. So you either have to have devices very close together or spaced by guardrings.
- Process restrictions require that every fin has to have an equal height. In addition there are strict limitations on the sizes of “W” and “L” that can be used. As a result a device that requires a large “W” (width) has to be quantized into multiple fin units that utilize the acceptable “W” and “L”.
What this means in practice is that an innocent-looking single device in the schematic can be 100 devices in the physical layout! Add to that the fact that fins have to snap to specific grids and you have a massive layout challenge for even a simple circuit.
Monday, February 15th, 2016
I left off in part 2 of this blog asking the question: “Have we exhausted all avenues in our search for layout productivity?”
Although there has been no revolutionary technology as with the initial CALMA systems, there have been some incremental improvements that help oil the gears when doing layout.
On-line DRC has been one such improvement. Having the ability to check the layout for design rule violations incrementally, as you complete more and more of the design, made it easier to implement changes. Violations were displayed in the layout, making it easy to find and fix them. However, checking the layout connectivity versus the schematic was still a batch task that could only be run when the design was fully implemented. The connectivity of the physical layout had to be extracted in order to compare against the logical connectivity.
As EDA marched on, with each new crop of more powerful workstations came the next generation of interactive tools. If you could compute the design rule checks fast enough, why not show them dynamically as layout geometries were being created? And so Design-Rule-Driven (DRD) layout was born.
Wednesday, February 10th, 2016
If I say ‘sticks’ to you, what comes to mind? Well, you could reply with “bits of wood” or “an American rock band from the 70’s” or “a river in Hades” and you would be correct. However, when you ask the question in the context of EDA, well, that’s a different story.
‘STICKS’ or ‘stick diagrams’ refers to a technology called symbolic layout. My first introduction to symbolic layout was the CALMA STICKS package that emerged around 1983.
STICKS was a netlist-driven symbolic design package that produced correct-by-construction physical layout directly from the logical netlist. Although a great concept, it never really took off. The effort to bring the logical connectivity into the layout by means of a netlist did not deliver a high-enough ROI in the eyes of the layout community.
Thursday, February 4th, 2016
It’s amazing what you find when you clean out your garage. I came across some old photographs of the first CALMA systems I worked on. Boy, have we come a long way since those days!
Those early CALMA Graphic Data Station (GDS) systems that I worked on back in the late 1970s were considered revolutionary. Why revolutionary? Well before they came along, making the masks for an IC was a real pain. Here’s a brief recap of what you had to do to:
Before GDS, the IC layout engineer would have to draw the circuits on large sheets of grid paper, using a different color for each layer of the circuit. Then they would produce a mask of each layer by cutting the shapes into a peel coat material such as Rubylith. To get a rectangle for example you would cut the four edges that made up the rectangle through the top layer of the Rubylith but not through the base layer. The peel coat material would be removed, leaving the rectangle exposed. The sheets were then photographically reduced to the real size of the IC. A stepper was then used to produce the physical masks by replicating the sheets as many times as would fit on a mask that was the real size of the wafer. Typical wafer sizes back then were around 4 inches. As you can imagine, this was very time consuming and very error-prone.