Posts Tagged ‘DRC’
Sunday, August 28th, 2016
In past blogs I provided some insights into the differences between FinFET and planar CMOS designs and why layout engineers need to take these differences seriously.
In introducing Custom Compiler, Synopsys has taken a fresh approach to custom design that employs visually-assisted automation technologies to speed up common design tasks, reduce iterations, and enable reuse. But sometimes, it’s not enough to simply say that a new tool is great–engineers need to see it to believe it.
As such, Synopsys has developed a collection of short technical webisodes focusing on the unique features of Custom Compiler’s visually-assisted automation technologies that can shorten FinFET design tasks from days to hours. The first webisode highlights how the symbolic editor enables layout engineers to create and optimize device placements at a high level of abstraction. We show how to rapidly create complex layout patterns for FinFET devices, as well as multi-row placements for PMOS and NMOS transistors, at a symbolic level without having to worry about design rules, connectivity or parameter values.
The second webisode highlights how Custom Compiler’s routing assistant enables layout engineers to route hundreds of connections with a simple click and drag of the mouse. We show how to rapidly route complex interdigitated layouts of FinFET devices, as well as simple multi-row placements for PMOS and NMOS transistors.
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Tags: Custom Comipiler, DRC, EDA, FinFET, routing, symbolic editor, Synopsys, webisode
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Monday, August 8th, 2016
DAC 2016 saw the first Synopsys custom design luncheon to feature Custom Compiler. It was a sold out event with 150 customer attendees eager to hear from Synopsys and other customers about how Synopsys is progressing in the custom design space. Antun Domic, Executive VP and General Manager of Synopsys’ Design Group moderated the event which included speakers from STMicroelectronics, GSI Technology, Samsung Foundry and the Synopsys IP team. For those of you who missed the live event, following is a short summary of the event highlights.
Antun opened the proceedings and presented Synopsys’ fresh approach to custom layout with Custom Compiler. He shared details of the pioneering visually-assisted automation technologies that speed up custom design tasks, reduce iterations and enable reuse.
Antun then went on to introduce each of the customer speakers who related their experiences using Custom Compiler and how visually-assisted automation helped them reduce their layout efforts from days to hours.
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Tags: 10nm, 14nm, 28nm, Custom Compiler, custom layout, DAC, DRC, EM/R, FD-SOI, FinFET, In-Design, low power, SRAM, Synopsys, visually-assisted automation
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Saturday, June 18th, 2016
On-line Design Rule Checking (DRC) is nothing new. The technology has been in use for years in a variety of different layout editors and yet nearly every layout engineer has a love/hate relationship with it. Why? Well it really comes down to the use model and the responsiveness of the application.
At the beginning of the design process, layout engineers love on-line DRC. But as the design progresses, the relationship begins to sour. The problem is that as the layout gets bigger and more complex, the performance invariably starts to fall off until it reaches a point where it becomes unacceptable and the layout engineer simply turns it off and resorts to running the occasional batch checks.
To really be effective, on-line DRC has to be an interactive tool that is run often during the layout process, so, as such it needs to have a simple use model and have a fast response. The engine needs to be ‘built-in’ to deliver the required performance and the feedback needs to be comprehensive enough to enable the layout engineer to quickly fix the violation.
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Tags: Custom Compiler, custom IC design, custom layout, design rule checking, DRC, EDA, FinFET, In-Design Assistant, Synopsys, violation, visually-assisted automation
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Wednesday, April 6th, 2016
So, hopefully, you are now aware of Synopsys’ new Custom Compiler solution tuned for rapid implementation of FinFET custom designs. Custom Compiler features a pioneering visually-assisted automation flow that speeds up custom design tasks from days to hours, reduces iterations and enables reuse–very exciting stuff!
But I want to continue my previous discussion thread to help you get a better understanding of the scope of the challenges inherent in FinFET design (and hopefully avoid some pitfalls).
So, going back to where I left off earlier… PCells for custom layout have been a ‘no brainer’ for decades. They have done all the heavy lifting with respect to generating correct-by-construction layout and have been the most important ‘power’ tool for custom layout engineers. Now however, given the complexity of the FinFET process, they become absolutely vital.
Generating a FinFET device is easy when you have a PCell. When coded correctly, it will automatically generate the device such that the fins are properly spaced on the requisite ‘fin grid’ and that all the rules for Poly width/length, Diffusion width/length, Poly cuts and the like are adhered to. In addition to constructing the device design rule correctly, the PCell will also ensure that the metals in the device are colored correctly and abide by the color-related rules. As you can imagine, there is a lot of stuff going on in a FinFET PCell, but there is more. FinFET PCells have to be ‘smarter than the average PCell’ and they have to be in tune with the layout methodology.
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Tags: correct-by-construction, Custom Compiler, custom layout, DRC, FinFET, iPDK, PCell, routability
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Wednesday, March 30th, 2016
Over the last few blogs I have outlined some of the productivity challenges that the FinFET process brings with respect to custom layout. Today Synopsys unveiled Custom Compiler and ushered in a new era of visually-assisted automation. Custom Compiler has all the good stuff I’ve been saying is needed in earlier posts: a new custom design solution that closes the FinFET productivity gap by shortening custom design tasks from days to hours.
This is not a revamp of the old constraint-based legacy approach, it’s a fresh approach to custom design that employs visually-assisted automation technologies to speed up common design tasks, reduce iterations and enable reuse.
What’s visually-assisted automation, you may ask?
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Tags: constraints, Custom Compiler, custom design, DRC, electromigration, EM/IR, FinFET, layout, SNUG, StarRC, Synopsys, visually-assisted automation
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Monday, February 15th, 2016
I left off in part 2 of this blog asking the question: “Have we exhausted all avenues in our search for layout productivity?”
Although there has been no revolutionary technology as with the initial CALMA systems, there have been some incremental improvements that help oil the gears when doing layout.
On-line DRC has been one such improvement. Having the ability to check the layout for design rule violations incrementally, as you complete more and more of the design, made it easier to implement changes. Violations were displayed in the layout, making it easy to find and fix them. However, checking the layout connectivity versus the schematic was still a batch task that could only be run when the design was fully implemented. The connectivity of the physical layout had to be extracted in order to compare against the logical connectivity.
As EDA marched on, with each new crop of more powerful workstations came the next generation of interactive tools. If you could compute the design rule checks fast enough, why not show them dynamically as layout geometries were being created? And so Design-Rule-Driven (DRD) layout was born.
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Tags: analog, CALMA, CMOS, custom design, DRC, DRD, EDA, FinFET, IC, layout, routing, SDL, SoC, Synopsys
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