Posts Tagged ‘symbolic editor’
Thursday, November 3rd, 2016
In the ‘Custom Compiler Layout Assistants (Part 1)’ blog post, I profiled the use of the symbolic editor and how it makes placing devices that need to be in a specific interdigitated pattern (for example, a differential pair) very easy. With no constraints to enter and no code to write, layout is done in minutes vs. hours.
However, there is a lot more to the symbolic editor than the ability to simplify interdigitation. One good example is the ability to define multiple P and N row pairs and then symbolically chain and fold the transistors such that you get them to fit neatly in the rows. This is a key feature that allows you to not only control the aspect ratio of the design, but to very rapidly create a custom digital cell layout, as shown in Figure 1.
Figure 1. Multiple Row Pairs
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Tags: analog, Custom Compiler, digital cell layout, FinFET, interdigitation, IP, layout, planar CMOS, symbolic editor, Synopsys, topology
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Sunday, August 28th, 2016
In past blogs I provided some insights into the differences between FinFET and planar CMOS designs and why layout engineers need to take these differences seriously.
In introducing Custom Compiler, Synopsys has taken a fresh approach to custom design that employs visually-assisted automation technologies to speed up common design tasks, reduce iterations, and enable reuse. But sometimes, it’s not enough to simply say that a new tool is great–engineers need to see it to believe it.
As such, Synopsys has developed a collection of short technical webisodes focusing on the unique features of Custom Compiler’s visually-assisted automation technologies that can shorten FinFET design tasks from days to hours. The first webisode highlights how the symbolic editor enables layout engineers to create and optimize device placements at a high level of abstraction. We show how to rapidly create complex layout patterns for FinFET devices, as well as multi-row placements for PMOS and NMOS transistors, at a symbolic level without having to worry about design rules, connectivity or parameter values.
The second webisode highlights how Custom Compiler’s routing assistant enables layout engineers to route hundreds of connections with a simple click and drag of the mouse. We show how to rapidly route complex interdigitated layouts of FinFET devices, as well as simple multi-row placements for PMOS and NMOS transistors.
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Tags: Custom Comipiler, DRC, EDA, FinFET, routing, symbolic editor, Synopsys, webisode
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Wednesday, June 15th, 2016
To all of you who attended DAC last week in Austin, TX–welcome back! I hope you were among the 175+ people who attended the Custom Compiler lunch event on Tuesday, June 7 to hear directly from engineers at GSI Technology, Samsung, STMicroelectronics and Synopsys’ IP group who described how Custom Compiler’s visually-assisted automation improves their productivity for both FinFET and established-node designs. We’ll be posting a videolog of the presentations on the Synopsys web site soon for those who missed the live event.
In the last blog I detailed the Symbolic Editor Layout Assistant and showed how the layout engineer can make simple graphical choices of how the layout needs to look and then have the placement taken care of by a placement engine. In this post I will outline another layout assistant: the Routing Assistant. The routing task is one that absolutely screams out for an automated approach, however past efforts have required a great deal of text-based constraints to get anything near to what you really want.
Custom Compiler’s Routing Assistant is a perfect combination of user guidance and automation. It’s a visually-assisted approach that allows the layout engineer to simply click on the starting point of the route and then drag the cursor in the direction they want the routing to follow. As the cursor moves along, behind the scenes the routing engine searches for connections that it can make. When it finds a connection it automatically taps to the pin without the layout engineer having to enter a mouse click. The user simply guides the router with the mouse and it fills in the routing details automatically.
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Tags: custom IC design, DAC, EDA, FinFET, layout productivity, routing, routing assistant, symbolic editor, Synopsys
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Wednesday, June 1st, 2016
As mentioned previously, on March 30th Silicon Valley was buzzing with excitement. Synopsys revealed Custom Compiler, a fresh approach to custom design that employs visually-assisted automation technologies to speed up common design tasks, reduce iterations and enable reuse at the SNUG Silicon Valley event. During this event, the R&D folks did a walkthrough of the technology ‘under-the-hood’ and showed the audience some cool layout assistants that leverage the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints. [Click here to view the videolog of the SNUG event.]
One of the layout assistants that was shown was the symbolic editor. This really is a must-have assistant when it comes to placing devices that need to be in a specific interdigitated pattern, like a differential pair. In the schematic, it is two symbols, but in the layout it could be hundreds of devices. The symbolic editor allows device placement to be edited in an easy and graphical manner and comes with a rich collection of predefined placement patterns. If you find a placement pattern you like, you can simply use it as-is and the symbolic editor will generate a correct-by-construction placement that you can instantiate in your layout. If you don’t find an exact match, you can easily use a pattern that is similar to what you need and rearrange the placement pattern graphically. No constraints to enter, no code to write and layout is done in minutes vs. hours.
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Tags: constraints, Custom Compiler, custom IC design, differential pair, FinFET, interdigitated pattern, layout, SNUG, symbolic editor, Synopsys, visually-assisted automation
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