Posts Tagged ‘EDA’
Sunday, August 28th, 2016
In past blogs I provided some insights into the differences between FinFET and planar CMOS designs and why layout engineers need to take these differences seriously.
In introducing Custom Compiler, Synopsys has taken a fresh approach to custom design that employs visually-assisted automation technologies to speed up common design tasks, reduce iterations, and enable reuse. But sometimes, it’s not enough to simply say that a new tool is great–engineers need to see it to believe it.
As such, Synopsys has developed a collection of short technical webisodes focusing on the unique features of Custom Compiler’s visually-assisted automation technologies that can shorten FinFET design tasks from days to hours. The first webisode highlights how the symbolic editor enables layout engineers to create and optimize device placements at a high level of abstraction. We show how to rapidly create complex layout patterns for FinFET devices, as well as multi-row placements for PMOS and NMOS transistors, at a symbolic level without having to worry about design rules, connectivity or parameter values.
The second webisode highlights how Custom Compiler’s routing assistant enables layout engineers to route hundreds of connections with a simple click and drag of the mouse. We show how to rapidly route complex interdigitated layouts of FinFET devices, as well as simple multi-row placements for PMOS and NMOS transistors.
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Tags: Custom Comipiler, DRC, EDA, FinFET, routing, symbolic editor, Synopsys, webisode
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Thursday, July 14th, 2016
Planning which metal shape goes on which color (mask) is key when designing in a FinFET process, especially when propagating connections through the layout hierarchy. In addition, highly matched signals such as complementary clocks must be assigned to the same color, as routes on different masks have different resistances. So how do we ensure we are keeping things in order with respect to the matching of resistance and capacitance?
Custom Compiler’s In-Design assistants include a built-in engine that computes resistance of a net from a single source to a single destination or multiple destinations. It is an interactive tool that can be run often during the layout process, has a simple use model and a fast response time. To report the resistance of a net, the layout engineer simply selects the net of interest from either the layout, the design navigator or the schematic. The next step is to invoke the resistance report command which pops up in the electrical report menu. The report type is set to “Resistance” and the source and destination points are entered. The report is run and the results are populated in the Electrical Reporter pane.
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Tags: capacitance, Custom Compiler, custom layout, EDA, FinFET, In-Design, LVS, metal mask, resistance, StarRC, Synopsys
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Saturday, June 18th, 2016
On-line Design Rule Checking (DRC) is nothing new. The technology has been in use for years in a variety of different layout editors and yet nearly every layout engineer has a love/hate relationship with it. Why? Well it really comes down to the use model and the responsiveness of the application.
At the beginning of the design process, layout engineers love on-line DRC. But as the design progresses, the relationship begins to sour. The problem is that as the layout gets bigger and more complex, the performance invariably starts to fall off until it reaches a point where it becomes unacceptable and the layout engineer simply turns it off and resorts to running the occasional batch checks.
To really be effective, on-line DRC has to be an interactive tool that is run often during the layout process, so, as such it needs to have a simple use model and have a fast response. The engine needs to be ‘built-in’ to deliver the required performance and the feedback needs to be comprehensive enough to enable the layout engineer to quickly fix the violation.
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Tags: Custom Compiler, custom IC design, custom layout, design rule checking, DRC, EDA, FinFET, In-Design Assistant, Synopsys, violation, visually-assisted automation
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Wednesday, June 15th, 2016
To all of you who attended DAC last week in Austin, TX–welcome back! I hope you were among the 175+ people who attended the Custom Compiler lunch event on Tuesday, June 7 to hear directly from engineers at GSI Technology, Samsung, STMicroelectronics and Synopsys’ IP group who described how Custom Compiler’s visually-assisted automation improves their productivity for both FinFET and established-node designs. We’ll be posting a videolog of the presentations on the Synopsys web site soon for those who missed the live event.
In the last blog I detailed the Symbolic Editor Layout Assistant and showed how the layout engineer can make simple graphical choices of how the layout needs to look and then have the placement taken care of by a placement engine. In this post I will outline another layout assistant: the Routing Assistant. The routing task is one that absolutely screams out for an automated approach, however past efforts have required a great deal of text-based constraints to get anything near to what you really want.
Custom Compiler’s Routing Assistant is a perfect combination of user guidance and automation. It’s a visually-assisted approach that allows the layout engineer to simply click on the starting point of the route and then drag the cursor in the direction they want the routing to follow. As the cursor moves along, behind the scenes the routing engine searches for connections that it can make. When it finds a connection it automatically taps to the pin without the layout engineer having to enter a mouse click. The user simply guides the router with the mouse and it fills in the routing details automatically.
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Tags: custom IC design, DAC, EDA, FinFET, layout productivity, routing, routing assistant, symbolic editor, Synopsys
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Wednesday, February 24th, 2016
In my last post, I said: “A hurricane has made landfall and its name is FinFET”. OK, it’s a little corny, but it was not meant to convey a sense of impending doom for custom layout productivity. No question that hurricanes are disruptive, but humans can adapt to even the worst nature can bring. And FinFETs bring tremendous benefits along with the disruption.FinFETs are without doubt the most radical shift in semiconductor technology in decades, but moving to FinFETs is absolutely necessary. As feature sizes became finer, high leakage current due to short-channel effects threatened to put the brakes on scaling. FinFETs address the leakage issue and give Moore’s Law a new lease of life.Today the bulk of design starts are at the established nodes above 28 nm, so not everyone doing custom layout has experience with FinFETs. For those who have not yet felt the ‘winds of change’ that FinFETs bring, here is a brief primer.
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Tags: 3D, custom design, EDA, FinFET, layout, Moore's Law, MOSFET, planar, SoC, Synopsys, UC Berkeley
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Monday, February 15th, 2016
I left off in part 2 of this blog asking the question: “Have we exhausted all avenues in our search for layout productivity?”
Although there has been no revolutionary technology as with the initial CALMA systems, there have been some incremental improvements that help oil the gears when doing layout.
On-line DRC has been one such improvement. Having the ability to check the layout for design rule violations incrementally, as you complete more and more of the design, made it easier to implement changes. Violations were displayed in the layout, making it easy to find and fix them. However, checking the layout connectivity versus the schematic was still a batch task that could only be run when the design was fully implemented. The connectivity of the physical layout had to be extracted in order to compare against the logical connectivity.
As EDA marched on, with each new crop of more powerful workstations came the next generation of interactive tools. If you could compute the design rule checks fast enough, why not show them dynamically as layout geometries were being created? And so Design-Rule-Driven (DRD) layout was born.
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Tags: analog, CALMA, CMOS, custom design, DRC, DRD, EDA, FinFET, IC, layout, routing, SDL, SoC, Synopsys
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Wednesday, February 10th, 2016
If I say ‘sticks’ to you, what comes to mind? Well, you could reply with “bits of wood” or “an American rock band from the 70’s” or “a river in Hades” and you would be correct. However, when you ask the question in the context of EDA, well, that’s a different story.
‘STICKS’ or ‘stick diagrams’ refers to a technology called symbolic layout. My first introduction to symbolic layout was the CALMA STICKS package that emerged around 1983.
STICKS was a netlist-driven symbolic design package that produced correct-by-construction physical layout directly from the logical netlist. Although a great concept, it never really took off. The effort to bring the logical connectivity into the layout by means of a netlist did not deliver a high-enough ROI in the eyes of the layout community.
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Tags: analog, correct-by-construction, custom, EDA, IC, schematic-driven layout, SDL, SoC, STICKS, Synopsys
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